XC2C128-7CPG132C Xilinx Inc, XC2C128-7CPG132C Datasheet - Page 8
![CPLD CoolRunner™-II Family 3K Gates 128 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 132-Pin CSBGA](/photos/6/70/67095/pk373-cp132_sml.jpg)
XC2C128-7CPG132C
Manufacturer Part Number
XC2C128-7CPG132C
Description
CPLD CoolRunner™-II Family 3K Gates 128 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 132-Pin CSBGA
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C128-7CPG132C
Package
132CSBGA
Family Name
CoolRunnerÂ-II
Device System Gates
3000
Number Of Macro Cells
128
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
100
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
152 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
0 to 70 °C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
3000
Number Of I /o
100
Mounting Type
Surface Mount
Package / Case
132-CSBGA
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1396
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C128-7CPG132C
Manufacturer:
XILINX
Quantity:
210
Company:
Part Number:
XC2C128-7CPG132C
Manufacturer:
TOREX
Quantity:
13 425
Company:
Part Number:
XC2C128-7CPG132C
Manufacturer:
CHRONTEL
Quantity:
19 350
Part Number:
XC2C128-7CPG132C
Manufacturer:
XILINX
Quantity:
20 000
XC2C128 CoolRunner-II CPLD
Internal Timing Parameters
8
Buffer Delays
T
T
T
T
T
T
T
P-term Delays
T
T
T
Macrocell Delay
T
T
T
T
T
T
T
T
T
Feedback Delays
T
T
I/O Standard Time Adder Delays 1.5V CMOS
T
T
T
I/O Standard Time Adder Delays 1.8V CMOS
T
T
T
T
OUT
AOI
OEM
OUT15
OUT18
IN
DIN
GCK
GSR
GTS
EN
CT
LOGI1
LOGI2
PDI
LDI
SUI
HI
ECSU
ECHO
COI
CDBL
F
HYS15
SLEW15
HYS18
IN18
SLEW18
Symbol
Input buffer delay
Direct data register input delay
Global Clock buffer delay
Global set/reset buffer delay
Global 3-state buffer delay
Output buffer delay
Output buffer enable/disable delay
Control term delay
Single P-term delay adder
Multiple P-term delay adder
Input to output valid
Setup before clock (transparent latch)
Setup before clock
Hold after clock
Enable clock setup time
Enable clock hold time
Clock to output valid
Set/reset to output valid
Clock doubler delay
Feedback delay
Macrocell to global OE delay
Hysteresis input adder
Output adder
Output slew rate adder
Hysteresis input adder
Input adder
Output adder
Output slew rate adder
Parameter
(1)
www.xilinx.com
Min.
1.4
0.0
1.4
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-6
Max.
2.0
3.7
1.5
1.6
2.1
2.3
3.8
1.2
0.5
0.3
0.9
2.1
0.4
1.1
0.0
1.8
2.0
3.0
0.8
4.0
2.0
0.0
2.5
0
-
-
-
-
Min.
1.4
0.0
1.6
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS093 (v3.2) March 8, 2007
-7
Product Specification
Max.
2.6
5.3
2.1
3.5
3.0
2.6
4.5
1.4
1.1
0.5
0.7
2.5
0.7
1.5
0.0
3.4
2.6
4.0
1.0
4.0
4.0
0.0
4.0
0
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R