M4A5-128/64-10VC LATTICE SEMICONDUCTOR, M4A5-128/64-10VC Datasheet - Page 9

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M4A5-128/64-10VC

Manufacturer Part Number
M4A5-128/64-10VC
Description
CPLD ispMACH™ 4A Family 5K Gates 128 Macro Cells 83.3MHz/118MHz EECMOS Technology 5V 100-Pin TQFP Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of M4A5-128/64-10VC

Package
100TQFP
Family Name
ispMACH™ 4A
Device System Gates
5000
Number Of Macro Cells
128
Maximum Propagation Delay Time
10 ns
Number Of User I/os
64
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
83.3|118 MHz
Number Of Product Terms Per Macro
20
Operating Temperature
0 to 70 °C

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M4A5-128/64-10VC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
M4A5-128/64-10VC
Manufacturer:
LATTICE
Quantity:
20 000
a. Basic cluster with XOR
b. Extended cluster, active high
c. Extended cluster, active low
0
d. Basic cluster routed away;
e. Extended cluster routed away
single-product-term, active high
17466G-007
Figure 3. Logic Allocator Configurations: Synchronous Mode
a. Basic cluster with XOR
b. Extended cluster, active high
c. Extended cluster, active low
0
d. Basic cluster routed away;
e. Extended cluster routed away
single-product-term, active high
17466G-008
Figure 4. Logic Allocator Configurations: Asynchronous Mode
Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All
configurations have the same delay. This means that designers do not have to decide between optimizing
resources or speed; both can be optimized.
If not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide
XOR logic for such functions as data comparison, or it can work with the D-,T-type flip-flop to provide
for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra
product term is still available for logic. In this case, the first XOR input will be a logic 0. This circuit has the
flexibility to route product terms elsewhere without giving up the use of the macrocell.
Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the ends of
the block have fewer product terms available.
ispMACH 4A Family
9

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