CY37064P100-125AXI Cypress Semiconductor Corp, CY37064P100-125AXI Datasheet - Page 12

• Manufacturer Part Number: CY37064P100-125AXI
• Description: CPLD Ultra37000™ Family 2K Gates 64 Macro Cells 125MHz CMOS Technology 5V 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultra37000™r

Specifications of CY37064P100-125AXI

• Package: 100TQFP
• Family Name: Ultra37000™
• Device System Gates: 2000
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 69
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 125 MHz
• Number Of Product Terms Per Macro: 16
• Operating Temperature: -40 to 85 °C
• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Macrocells: 64
• Number Of I /o: 69
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Voltage: 5V
• Memory Type: CMOS
• # Macrocells: 64
• Number Of Usable Gates: 2000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• # I/os (max): 69
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-1936; CY37064P100-125AXI

Document #: 38-03007 Rev. *E
Logic Block Diagrams
CY37384/CY37384V
TDI
TCK
TMS
JTAG Tap
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
36
48
60
72
84
12
24
0
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
47
59
71
83
95
11
23
35
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
(continued)
TDO
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
4
AG
AH
AC
AD
AE
AF
AK
AA
AB
AJ
AL
AI
96
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
Input
1
PIM
Clock/
Input
4
36
16
36
16
36
16
36
16
36
16
36
16
36
16
16
36
16
36
16
36
16
36
16
36
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
96
BH
BG
BF
BE
BD
BC
BB
BA
BK
BL
BJ
BI
4
Ultra37000 CPLD Family
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
132
120
108
96
96
168
156
144
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
119
107
155
143
131
191
179
167
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