LM117K/883 National Semiconductor, LM117K/883 Datasheet - Page 12

• Manufacturer Part Number: LM117K/883
• Description: Standard Regulator Pos 1.2V to 37V 1.5A 3-Pin (2+Tab) TO-3 Bag
• Manufacturer: National Semiconductor
• Type: Linearr

Specifications of LM117K/883

• Package: 3TO-3
• Function: Standard
• Number Of Outputs: 1
• Input Voltage Range: 41.25 to 4.25 V
• Output Voltage: 1.2 to 37 V
• Maximum Output Current: 1.5 A
• Output Type: Adjustable
• Operating Temperature: -55 to 125 °C
• Polarity: Positive
• Reference Voltage: 1.3 V
• Voltage Regulator Type: Linear
• Topology: Standard
• Regulator Output Type: Adjustable
• Polarity Type: Positive
• Input Voltage (min): 4.25V
• Input Voltage (max): 41.25V
• Package Type: TO-3
• Output Current: 1.5A
• Power Dissipation: 20W
• Load Regulation: 0.3%
• Line Regulation: 22.2mV
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Pin Count: 2 +Tab
• Mounting: Through Hole
• Lead Free Status / Rohs Status: Not Compliant

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
(maximum junction temperature), θ
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(package
Jmax
JA
)/
junction to ambient thermal resistance), and T
(ambient temperature). The maximum allowable power dissipation at any temperature is P
= (T
- T
A
Dmax
Jmax
A
θ
or the number given in the Absolute Maximum Ratings, whichever is lower. "Although power dissipation is internally limited, these specifications are applicable
JA
for power dissipations of 2W for the TO39, LCC, and ceramic SOIC packages, and 20W for the TO3 package."
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: For the Ceramic SOIC device to function properly, the “Output” and “Output/Sense” pins must be connected on the users printed circuit board.
Note 6: The package material for these devices allows much improved heat transfer over our standard ceramic packages. In order to take full advantage of this
improved heat transfer, heat sinking must be provided between the package base (directly beneath the die), and either metal traces on, or thermal vias through,
the printed circuit board. Without this additional heat sinking, device power dissipation must be calculated using θ
, rather than θ
, thermal resistance. It must
JA
JC
not be assumed that the device leads will provide substantial heat transfer out the package, since the thermal resistance of the leadframe material is very poor,
relative to the material of the package base. The stated θ
thermal resistance is for the package material only, and does not account for the additional thermal
JC
resistance between the package base and the printed circuit board. The user must determine the value of the additional thermal resistance and must combine
this with the stated value for the package, to calculate the total allowed power dissipation for the device.
Note 7: Guaranteed parameter, not tested.
Note 8: Tested @ 25°C; guaranteed, but not tested @ 125°C & −55°C
Note 9: Tested @ T
= 125°C, correlated to T
= 150°C
A
A
Note 10: SMD limit of 6mV/V is equivalent to 18mV
Note 11: SMD limit of 0.3mV/V is equivalent to 120mV
Note 12: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the “Post Radiation Limits” table.
These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters
are guaranteed only for the conditions as specified in Mil-Std-883, Method 1019.5, Condition A.
Note 13: Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019 condition D of MIL-STD-883, with no enhanced low dose
rate sensitivity (ELDRS) effect.
Typical Performance Characteristics
Output Capacitor = 0μF unless otherwise noted
Load Regulation
Current Limit
20143637
20143638
www.national.com
12