72261LA15TFI Integrated Device Technology (Idt), 72261LA15TFI Datasheet - Page 25

• Manufacturer Part Number: 72261LA15TFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 9 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72261LA15TFI

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 144 Kb
• Organization: 16Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: -40 to 85 °C

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 16,384 and 32,768 for the IDT72271LA with a 9-bit bus width.
In FWFT mode, the FIFOs can be connected in series (the data outputs of one
FIFO connected to the data inputs of the next) with no external logic necessary.
The resulting configuration provides a total depth equivalent to the sum of the
depths associated with each single FIFO. Figure 22 shows a depth expansion
using two IDT72261LA/72271LA devices.
FIFOs in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the
data word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
FWFT/SI
WRITE ENABLE
INPUT READY
DATA IN
WRITE CLOCK
The IDT72261LA can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all
For an empty expansion configuration, the amount of time it takes for OR of
n
(N – 1)*(4*transfer clock) + 3*T
Dn
WEN
IR
WCLK
FWFT/SI
72261LA
72271LA
Figure 20. Block Diagram of 32,768 x 9 and 65,536 x 9 Depth Expansion
IDT
TRANSFER CLOCK
RCLK
RCLK
REN
OE
OR
Qn
RCLK
is the RCLK
SKEW3
GND
n
25
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in
one FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding
FIFO to write a word to fill it.
FIFO in the chain to go LOW after a word has been read from the last FIFO
is the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the
t
and transfer clock, for the IR flag.
whichever is faster. Both these actions result in data moving, as quickly
as possible, to the end of the chain and free locations to the beginning of
the chain.
SKEW1
The "ripple down" delay is only noticeable for the first word written to an
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR of the first
The Transfer Clock line should be tied to either WCLK or RCLK,
specification is not met between RCLK and transfer clock, or WCLK
WCLK
IR
WEN
Dn
(N – 1)*(3*transfer clock) + 2 T
FWFT/SI
72261LA
72271LA
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
TEMPERATURE RANGES
OR
OE
Qn
WCLK
JANUARY 7, 2009
OUTPUT ENABLE
n
OUTPUT READY
WCLK
READ ENABLE
READ CLOCK
DATA OUT
is the WCLK
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