72V2113L7-5BCI Integrated Device Technology (Idt), 72V2113L7-5BCI Datasheet - Page 40

• Manufacturer Part Number: 72V2113L7-5BCI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 256K x 18/512K x 9 100-Pin CABGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V2113L7-5BCI

• Package: 100CABGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 4.5 Mb
• Organization: 256Kx18|512Kx9
• Data Bus Width: 18|9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 131,072 when the x18 Input or x18 Output bus Width is selected
and 262,144 for the IDT72V2113. When both x9 Input and x9 Output bus Widths
are selected, depths greater than 262,144 can be adapted for the IDT72V2103
and 524,288 for the IDT72V2113. In FWFT mode, the FIFOs can be connected
in series (the data outputs of one FIFO connected to the data inputs of the next)
with no external logic necessary. The resulting configuration provides a total
depth equivalent to the sum of the depths associated with each single FIFO.
Figure 30 shows a depth expansion using two IDT72V2103/72V2113 devices.
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
where N is the number of FIFOs in the expansion and T
Note that extra cycles should be added for the possibility that the t
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
The IDT72V2103 can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all FIFOs
For an empty expansion configuration, the amount of time it takes for OR of
DATA IN
FWFT/SI
WRITE ENABLE
WRITE CLOCK
INPUT READY
n
(N – 1)*(4*transfer clock) + 3*T
IR
Dn
WCLK
WEN
For both x9 Input and x9 Output bus Widths: 524,288 x 9 and 1,048,576 x 9
For the x18 Input or x18 Output bus Width: 262,144 x 18 and 524,288 x 18
FWFT/SI
72V2103
72V2113
IDT
TRANSFER CLOCK
Figure 30. Block Diagram of Depth Expansion
RCLK
RCLK
RCLK
REN
OE
Qn
OR
is the RCLK period.
TM
NARROW BUS FIFO
SKEW1
TM
GND
NARROW BUS FIFO
40
n
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling the
preceding FIFO to write a word to fill it.
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
The "ripple down" delay is only noticeable for the first word written to an
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR of the first
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
IR
WCLK
WEN
Dn
(N – 1)*(3*transfer clock) + 2 T
72V2103
72V2113
FWFT/SI
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
OR
OE
Qn
TEMPERATURE RANGES
WCLK
OUTPUT READY
OUTPUT ENABLE
n
READ ENABLE
WCLK
READ CLOCK
JUNE 1, 2010
DATA OUT
is the WCLK
6119 drw33
SKEW1