MT48LC8M16A2TG-7E:G Micron Technology Inc, MT48LC8M16A2TG-7E:G Datasheet - Page 62

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MT48LC8M16A2TG-7E:G

Manufacturer Part Number
MT48LC8M16A2TG-7E:G
Description
DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC8M16A2TG-7E:G

Density
128 Mb
Maximum Clock Rate
143 MHz
Package
54TSOP-II
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
5.4 ns
Operating Temperature
0 to 70 °C
Organization
8Mx16
Address Bus
14b
Access Time (max)
5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
165mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC8M16A2TG-7E:G
Manufacturer:
MIC
Quantity:
6 000
Part Number:
MT48LC8M16A2TG-7E:G
Manufacturer:
MIC
Quantity:
6 000
Part Number:
MT48LC8M16A2TG-7E:G
Manufacturer:
MICRON
Quantity:
8 000
Figure 46:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMH
A0–A9, A11
COMMAND
BA0, BA1
DQM /
CLK
A10
CKE
DQ
t CMS
t CKS
t AS
t AS
t AS
Alternating Bank Read Accesses
ACTIVE
BANK 0
T0
ROW
ROW
t CMH
t CKH
t AH
t AH
t AH
Notes:
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
t CK
T1
1. For this example, BL = 4, and CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
NOP
x8: A11 = “Don’t Care.”
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
BANK 0
T2
READ
t CMH
t CH
CAS Latency - BANK 0
T3
NOP
t LZ
t AC
62
BANK 3
ACTIVE
T4
ROW
ROW
D
OUT
t OH
t AC
m
t RCD - BANK 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
T5
OUT
NOP
m + 1
t OH
t AC
ENABLE AUTO PRECHARGE
COLUMN b 2
BANK 3
D
T6
OUT
128Mb: x4, x8, x16 SDRAM
READ
m + 2
t OH
t AC
CAS Latency - BANK 3
©1999 Micron Technology, Inc. All rights reserved.
t RP - BANK 0
D
T7
NOP
OUT
Timing Diagrams
m + 3
t OH
t AC
BANK 0
T8
ACTIVE
ROW
ROW
DON’T CARE
UNDEFINED
D
OUT
t RCD - BANK 0
t OH
t AC
b

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