MT48LC4M16A2P-75:G TR Micron Technology Inc, MT48LC4M16A2P-75:G TR Datasheet - Page 56

• Manufacturer Part Number: MT48LC4M16A2P-75:G TR
• Description: DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M16A2P-75:G TR

• Density: 64 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Organization: 4Mx16
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1088-2

Figure 39:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
Self Refresh Mode
COMMAND
A0–A9, A11
BA0, BA1
DQM/
Notes:
CKE
A10
CLK
DQ
High-Z
Precharge all
t CKS
active banks
t CMS
SINGLE BANK
t
AS
PRECHARGE
ALL BANKS
BANK(S)
T0
1. No maximum time limit for self refresh mode.
2.
3. Self refresh mode not supported on automotive temperature (AT) devices.
t CKH
t CMH
t
AH
t CK
t
XSR requires minimum of two clocks regardless of frequency and timing.
t RP
T1
NOP
t CH
Enter self refresh mode
t CKS
t CL
REFRESH
AUTO
CLK stable prior to exiting
T2
self refresh mode
≥
t RAS(MIN)
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(Restart refresh time base)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Exit self refresh mode
Tn + 1
NOP
t XSR
t
RAS(MAX) applies to non-self refresh mode.
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or COMMAND
INHIBIT
To + 1
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
To + 2
REFRESH
AUTO
Timing Diagrams
DON’T CARE