MT48LC4M16A2P-75:G Micron Technology Inc, MT48LC4M16A2P-75:G Datasheet - Page 37

• Manufacturer Part Number: MT48LC4M16A2P-75:G
• Description: DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC4M16A2P-75:G

• Density: 64 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Organization: 4Mx16
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP (0.400", 10.16mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

READ with Auto Precharge
WRITE with Auto Precharge
Figure 29:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
READ With Auto Precharge Interrupted by a READ
Note:
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
Internal
States
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 29 on page 37).
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 30 on page 38).
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 31 on page 38).
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 32 on page 39).
DQM is LOW.
t
WR is met, where
COMMAND
ADDRESS
BANK m
BANK n
CLK
DQ
Page Active
T0
NOP
t
WR begins when the WRITE to bank m is registered. The last
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
37
READ with Burst of 4
CAS Latency = 3 (BANK n)
T2
NOP
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WR is met, where
BANK m,
READ - AP
T3
BANK m
COL d
Interrupt Burst, Precharge
CAS Latency = 3 (BANK m)
READ with Burst of 4
TRANSITIONING DATA
T4
NOP
D
64Mb: x4, x8, x16 SDRAM
a
OUT
t
RP - BANK n
t
WR begins when the READ to
T5
NOP
©2000 Micron Technology, Inc. All rights reserved.
D
a + 1
OUT
T6
NOP
D
OUT
d
Commands
DON’T CARE
Idle
T7
NOP
t RP - BANK m
Precharge
D
d + 1
OUT