MT46V16M16P-6T IT:K Micron Technology Inc, MT46V16M16P-6T IT:K Datasheet - Page 84
![DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 66-Pin TSOP Tray](/photos/31/34/313420/66pin_tsop_sml.jpg)
MT46V16M16P-6T IT:K
Manufacturer Part Number
MT46V16M16P-6T IT:K
Description
DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.5V 66-Pin TSOP Tray
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V16M16P-6T_ITK.pdf
(93 pages)
Specifications of MT46V16M16P-6T IT:K
Density
256 Mb
Maximum Clock Rate
333 MHz
Package
66TSOP
Address Bus Width
15 Bit
Operating Supply Voltage
2.5 V
Maximum Random Access Time
0.7 ns
Operating Temperature
-40 to 85 °C
Organization
16Mx16
Address Bus
15b
Access Time (max)
700ps
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
220mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
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Figure 47:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
Address
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
Bank a,
Notes:
WRITE
Col b
T0
t DQSS
t DQSS
t DQSS
1. DI b = data-in for column b.
2. An interrupted burst of 8 is shown; one data element is written.
3.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T4 and T4n (nominal case) to register DM.
6. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
t
DI
b
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
DI
T1
b
DI
b
T1n
NOP
T2
T2n
t WR
82
NOP
T3
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(a or all)
Bank,
T4
PRE
256Mb: x4, x8, x16 DDR SDRAM
T4n
Transitioning Data
T5
NOP
©2003 Micron Technology, Inc. All rights reserved.
t RP
T6
NOP
Operations
Don’t Care
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