MT46V16M16P-5B:K TR Micron Technology Inc, MT46V16M16P-5B:K TR Datasheet - Page 78
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MT46V16M16P-5B:K TR
Manufacturer Part Number
MT46V16M16P-5B:K TR
Description
DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP T/R
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V16M16CY-5BK_TR.pdf
(93 pages)
Specifications of MT46V16M16P-5B:K TR
Package
66TSOP
Density
256 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
2.6 V
Maximum Clock Rate
400 MHz
Maximum Random Access Time
0.7 ns
Operating Temperature
0 to 70 °C
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Figure 40:
Figure 41:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Nonconsecutive WRITE-to-WRITE
Random WRITE Cycles
Notes:
Notes:
t DQSS (NOM)
1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
Command
1. DI b (or x or n or a or g) = data-in from column b (or column x, or column n, or column a, or
2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g,
3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown.
4. Each WRITE command may be to any bank.
Address
Command
column g).
respectively.
Address
DQS
CK#
DM
DQ
CK
DQS
CK#
DM
DQ
CK
WRITE
Bank,
Col b
T0
WRITE
Bank,
Col b
T0
t DQSS (NOM)
t DQSS
WRITE
Bank,
Col x
DI
T1
b
NOP
DI
T1
b
76
T1n
DI
b'
T1n
WRITE
Bank,
Col n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
DI
x
NOP
T2
T2n
DI
x'
T2n
256Mb: x4, x8, x16 DDR SDRAM
WRITE
Bank,
Col a
T3
DI
n
WRITE
Bank,
Col n
T3
Transitioning Data
T3n
DI
n'
Transitioning Data
©2003 Micron Technology, Inc. All rights reserved.
WRITE
Bank,
Col g
T4
DI
a
NOP
DI
T4
n
T4n
DI
a'
T4n
Operations
NOP
T5
DI
g
Don’t Care
T5
NOP
Don’t Care
T5n
DI
g'
T5n
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