8543BGILF Integrated Device Technology (Idt), 8543BGILF Datasheet

no-image

8543BGILF

Manufacturer Part Number
8543BGILF
Description
Clock Driver 2-IN LVDS 20-Pin TSSOP Tube
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 8543BGILF

Package
20TSSOP
Configuration
1 x 2:1
Input Signal Type
CML/HCSL/LVDS/LVHSTL/LVPECL/SSTL
Maximum Output Frequency
650 MHz
Operating Supply Voltage
3.3 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
8543BGILF
Manufacturer:
IDT
Quantity:
100
Part Number:
8543BGILFT
Manufacturer:
IDT
Quantity:
20 000
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS
FANOUT BUFFER
General Description
provides a low power, low noise, solution for distributing clock
signals over controlled impedances of 100Ω. The ICS8543I has
two selectable clock inputs. The CLK, nCLK pair can accept most
standard differential input levels. The PCLK, nPCLK pair can
accept LVPECL, CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8543I ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
IDT™ / ICS™ LVDS FANOUT BUFFER
HiPerClockS™
CLK_SEL
ICS
CLK_EN
nPCLK
PCLK
nCLK
CLK
OE
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
The ICS8543I is a low skew, high performance
1-to-4 Differential-to-LVDS Clock Fanout Buffer and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. Utilizing Low
Voltage Differential Signaling (LVDS) the ICS8543I
0
1
0
1
D
LE
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
Features
Four differential LVDS output pairs
Selectable differential CLK/nCLK or LVPECL clock inputs
CLK/nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
PCLK/nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
Maximum output frequency: 650MHz
Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
Additive phase Jitter, RMS: 0.164ps (typical)
Output skew: 40ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 2.6ns (maximum)
Full 3.3Vsupply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
6.5mm x 4.4mm x 0.925
CLK_SEL
CLK_EN
nPCLK
PCLK
nCLK
GND
GND
CLK
V
20-Lead TSSOP
OE
DD
package body
G Package
ICS8543BGI REV. E SEPTEMBER 9, 2008
Top View
ICS8543I
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
V
Q1
nQ1
nQ2
Q3
nQ0
Q2
nQ3
DD
mm
ICS8543I

Related parts for 8543BGILF

8543BGILF Summary of contents

Page 1

LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER General Description The ICS8543I is a low skew, high performance ICS 1-to-4 Differential-to-LVDS Clock Fanout Buffer and a member of the HiPerClockS™ family of High HiPerClockS™ Performance Clock Solutions from IDT. Utilizing Low Voltage ...

Page 2

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Table 1. Pin Descriptions Number Name GND Power 2 CLK_EN Input 3 CLK_SEL Input 4 CLK Input 5 nCLK Input 6 PCLK Input 7 nPCLK Input 8 OE Input 10, ...

Page 3

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Function Tables Table 3A. Control Input Function Table OE CLK_EN After CLK_EN switches, the clock outputs are disabled or enabled following a rising ...

Page 4

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or ...

Page 5

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Table 4C. Differential DC Characteristics, V Symbol Parameter CLK I Input High Current IH nCLK CLK I Input Low Current IL nCLK V Peak-to-Peak Voltage; NOTE 1 PP Common Mode Input Voltage; V ...

Page 6

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER AC Electrical Characteristics Table 5. AC Characteristics Parameter Symbol f Maximum Output Frequency MAX Buffer Additive Phase Jitter, RMS; tjit refer to Additive Phase Jitter Section t Propagation Delay; NOTE 1 ...

Page 7

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally ...

Page 8

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Parameter Measurement Information V DD 3.3V±5% POWER SUPPLY LVDS + – Float GND 3.3V LVDS Output Load AC Test Circuit V DD nQ[0:3] V Cross Points OD Q[0: GND Differential Output ...

Page 9

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Parameter Measurement Information, continued nQ[0:3] 80% 20% Q[0: Output Rise/Fall Time V DD LVDS DC Input ➤ Offset Voltage Setup 3.3V±5% POWER SUPPLY LVDS Inpu Float GND + ...

Page 10

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Parameter Measurement Information, continued V DD LVDS DC Input Output Short Circuit Current Setup Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can ...

Page 11

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the V V input requirements. Figures show interface CMR ...

Page 12

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both signals must meet the V requirements. Figures show interface examples for the HiPerClockS PCLK/nPCLK ...

Page 13

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for ...

Page 14

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8543I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8543I is ...

Page 15

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Reliability Information Table 7. θ vs. Air Flow Table for a 20 Lead TSSOP JA Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count ...

Page 16

... ICS8543BGILF 8543BGILFT ICS8543BGILF NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 17

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Revision History Sheet Rev Table Page Description of Change A 3 Updated Figure 1, CLK_EN Timing Diagram Updated Figure 1, CLK_EN Timing Diagram. 1 Features section, Bullet 6 to read 3.3V ...

Page 18

ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Contact Information: www.IDT.com Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT ...

Related keywords