QS3VH244PAG8 Integrated Device Technology (Idt), QS3VH244PAG8 Datasheet - Page 7

• Manufacturer Part Number: QS3VH244PAG8
• Description: Bus Switch 2-Element 4-IN 20-Pin TSSOP T/R
• Manufacturer: Integrated Device Technology (Idt)

Specifications of QS3VH244PAG8

• Package: 20TSSOP
• Configuration: 4 x 1:1
• Logic Function: Bus Switch
• Number Of Elements Per Chip: 2
• Number Of Outputs Per Chip: 8
• Typical Operating Supply Voltage: 2.5|3.3 V
• Maximum On Resistance: 7(Typ) Ohm
• Maximum Low Level Output Current: 120 mA
• Maximum Operating Supply Voltage: 3.6 V
• Minimum Operating Supply Voltage: 2.3 V
• Maximum Propagation Delay Time @ Maximum Cl: 0.2@3.3V ns

TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
DEFINITIONS:
C
R
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; t
SWITCH POSITION
Pulse
Generator
IDTQS3VH244
2.5V / 3.3V 8-BIT HIGH BANDWIDTH BUS SWITCH
L
T
= Termination resistance: should be equal to Z
= Load capacitance: includes jig and probe capacitance.
Symbol
V
(1, 2)
V
V
LOAD
V
V
C
HZ
LZ
IH
T
L
t
t
PHZ/
PLZ
Test
t
V
PD
/
t
t
PZH
IN
PZL
V
CC
Test Circuits for All Outputs
(1)
= 3.3V ± 0.3V
300
300
1.5
R
50
6
3
T
D.U.T.
V
CC
V
OUT
V
OUT
CC
F
F
≤ 2ns; t
(2)
≤ 2.5ns; t
of the Pulse Generator.
C
= 2.5V ± 0.2V
2 x Vcc
V
L
Vcc
150
150
CC
30
Switch
V
/2
R
GND
Open
LOAD
R
≤ 2ns.
500
500
≤ 2.5ns.
Ω
Ω
GND
V
Open
Unit
mV
mV
pF
V
V
V
LO AD
7
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
INPUT TRANSITIO N
INPUT TRANSITION
O PPO SITE PHASE
NORM ALLY
NORM ALLY
CO NTROL
OUTPUT
OUTPUT
SAM E PHASE
INPUT
HIGH
LO W
OUTPUT
C LOSED
SW ITCH
SW ITCH
Enable and Disable Times
ENABLE
O PEN
Propagation Delay
t
t
PZH
PZL
t
t
INDUSTRIAL TEMPERATURE RANGE
P LH
PLH
V
0V
V
V
T
T
LO AD/2
t
PHZ
DISABLE
t
t
PHL
P HL
t
P LZ
V
V
0V
V
V
V
V
V
0V
V
V
0V
V
V
V
V
V
0V
IH
T
LO A D/2
O L +
O L
O H
O H -
IH
T
OH
T
O L
IH
T
V
V
H Z
LZ