QS3VH16211PAG8 Integrated Device Technology (Idt), QS3VH16211PAG8 Datasheet - Page 7

• Manufacturer Part Number: QS3VH16211PAG8
• Description: Bus Switch 2-Element 12-IN 56-Pin TSSOP T/R
• Manufacturer: Integrated Device Technology (Idt)

Specifications of QS3VH16211PAG8

• Package: 56TSSOP
• Configuration: 12 x 1:1
• Logic Function: Bus Switch
• Number Of Elements Per Chip: 2
• Number Of Outputs Per Chip: 24
• Typical Operating Supply Voltage: 2.5|3.3 V
• Maximum On Resistance: 7(Typ) Ohm
• Maximum High Level Output Current: -120 mA
• Maximum Low Level Output Current: 120 mA
• Maximum Operating Supply Voltage: 3.6 V
• Minimum Operating Supply Voltage: 2.3 V
• Maximum Propagation Delay Time @ Maximum Cl: 0.2@3.3V ns

TEST CIRCUITS AND WAVEFORMS
DEFINITIONS:
C
R
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
SWITCH POSITION
TEST CONDITIONS
IDTQS3VH16211
2.5V / 3.3V 24-BIT HIGH BANDWIDTH BUS SWITCH
Pulse
Generator
L
T
Symbol
= Termination resistance: should be equal to Z
V
= Load capacitance: includes jig and probe capacitance.
V
V
LOAD
V
V
C
HZ
LZ
IH
T
L
(1, 2)
V
CC
V
t
t
PHZ/
PLZ
Test
IN
(1)
t
PD
/
= 3.3V ± 0.3V
t
t
PZL
PZH
Test Circuits for All Outputs
300
300
1.5
50
6
3
R
T
D.U.T.
V
CC
V
OUT
V
CC
OUT
F
F
(2)
≤ 2ns; t
= 2.5V ± 0.2V
≤ 2.5ns; t
2 x Vcc
of the Pulse Generator.
C
V
Switch
V
Vcc
150
150
L
GND
Open
CC
30
LOAD
/2
R
500
500
R
≤ 2ns.
≤ 2.5ns.
Ω
Ω
V
Open
GND
Unit
mV
mV
LOAD
pF
V
V
V
7
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
NORMALLY
NORM ALLY
CONTROL
OUTPUT
OUTPUT
SAM E PHASE
INPUT
HIGH
LOW
OUTPUT
CLO SED
SW ITCH
SW ITCH
Enable and Disable Times
ENABLE
OPEN
Propagation Delay
t
t
PZH
PZL
t
t
PLH
PLH
INDUSTRIAL TEMPERATURE RANGE
V
0V
V
V
T
T
LOAD/2
t
PHZ
DISABLE
t
t
PHL
PHL
t
PLZ
V
V
0V
V
V
V
V
V
0V
V
0V
V
0V
V
V
V
V
V
IH
T
LO AD /2
O L +
O L
O H
O H -
IH
T
OH
T
OL
IH
T
V
V
H Z
L Z