PEX 8618-BA50BC G PLX Technology, PEX 8618-BA50BC G Datasheet

PEX 8618-BA50BC G

Manufacturer Part Number

PEX 8618-BA50BC G

Description

PCI Express Switch 324-Pin HSBGA

Manufacturer

PLX Technology

Datasheet

1.PEX8618BA-BB4U1DRDK.pdf (4 pages)

Specifications of PEX 8618-BA50BC G

Package

324HSBGA

Current page: 1 of 4
Download datasheet (729Kb)

Features

PEX 8618 General Features

o 16-lane PCI Express switch

o Up to 16 configurable ports

o 19 x 19mm

o Typical Power: 1.93 Watts

PEX 8618 Key Features

o Standards Compliant

o High Performance

o Dual-Host & Fail-Over Support

o Flexible Configuration

o PCI Express Power Management

o Spread Spectrum Clock Isolation

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

- Integrated 5.0 GT/s SerDes

- PCI Express Base Specification r2.0

- PCI Power Management Spec r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Non-blocking internal architecture

- Full line rate on all ports

- Cut-Thru latency: 140ns

- 2KB max payload size

- Read Pacing

- Dual Cast

- Configurable Non-Transparent port

- Moveable upstream port

- Crosslink port capability

- 16 flexible & configurable ports

- Configurable with strapping pins,

- Lane and polarity reversal

- Link power management states: L0, L0s,

- Device states: D0 and D3

- Dual clock domain

- Two Virtual Channels (VC) per port

- Eight Traffic Classes per port

- Weighted Round-Robin Port & VC

- All ports Hot-Plug capable thru I

- ECRC & Poison bit support

- Data path protection

- Memory (RAM) error correction

- Advanced Error Reporting support

- Port Status bits and GPIO available

- Per port error diagnostics

- Performance monitoring

- JTAG AC/DC boundary scan

- Fatal Error (FATAL_ERR#) output signal

(Backwards compatible with PCIe

r1.0a/1.1)

(intelligent bandwidth allocation)

(NTB)

(x1, x4, or x8)

EEPROM, I

L1, L2/L3 Ready, and L3

Arbitration

(Hot-Plug Controller on every port)

(per port payload & header counters)

INTA# output signal

Version 1.2 2009

, 324-ball HSBGA

C, or Host software

hot

The ExpressLane

enabling users to add scalable high bandwidth non-blocking interconnection to a

wide variety of applications including control planes, communication platforms,

servers, storage systems and embedded systems. The PEX 8618 is well suited for

fan-out, aggregation, peer-to-peer, and intelligent I/O module applications

Low Packet Latency & High Performance

The PEX 8618 architecture supports packet cut-thru with a maximum latency of

140ns. This, combined with large packet memory and non-blocking internal switch

architecture, provides full line rate on all ports for low-latency applications such as

communications and servers. The low latency enables applications to achieve high

throughput and performance. In addition to low latency, the device supports a max

payload size of 2048 bytes, enabling the user to achieve even higher throughout

Data Integrity

The PEX 8618 provides end-to-end CRC protection (ECRC) and Poison bit support

to enable designs that require guaranteed error-free packets. PLX also supports

data path parity and memory (RAM) error correction as packets pass through the

switch

Dual-Host and Fail-Over Support

The PEX 8618 supports full non-transparent bridging (NTB) functionality to allow

implementation of multi-host systems and intelligent I/O modules in applications

which require redundancy support such as communications, storage, and servers.

Non-transparent bridges allow systems to isolate host memory domains by

presenting the processor subsystem as an endpoint rather than another memory

system. Base address registers are used to translate addresses; doorbell registers are

used to send interrupts between the address domains; and scratchpad registers are

accessible from both address domains to allow inter-processor communication

Interoperability

The PEX 8618 is designed to be fully compliant with the PCI Express Base

Specification r2.0 and is backwards compatible to PCI Express Base Specification

r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and

polarity reversal. Furthermore, the PEX 8618 is designed for Microsoft Vista

compliance. All PLX switches undergo thorough interoperability testing in PLX’s

Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure

compatibility with PCI Express devices in the market.

Device Operation Configuration Flexibility

The PEX 8618 provides several ways to configure its operations. The device can be

configured through strapping pins, I

optional serial EEPROM. This allows for easy debug during the development phase

and functional monitoring during the operation phase

Flexible & Versatile 16-lane 16-port PCI Express

PEX 8618

™

PEX 8618 device offers PCI Express switching capability

C interface, CPU configuration cycles and/or an

Switch

Related parts for PEX 8618-BA50BC G

PEX 8618-BA50BC G Summary of contents

Page 1

... Interoperability The PEX 8618 is designed to be fully compliant with the PCI Express Base Specification r2.0 and is backwards compatible to PCI Express Base Specification r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and polarity reversal. Furthermore, the PEX 8618 is designed for Microsoft Vista compliance. All PLX switches undergo thorough interoperability testing in PLX’ ...

Page 2

... PCI slots or Generic devices through the use of the PEX 8311 and PEX 8112 PCIe bridging devices. Control Plane Application The PEX 8618 is ideal for control planes in routers and other communications sub-systems to meet increased packet processing needs without compromising latency. Figure 3 ...

Page 3

... CPU. The PEX 8618 non-transparent port allows the two CPUs to be isolated but communicate with each other through various registers that are designed in the PEX 8618 for that purpose. The host CPU can dynamically re-assign both the upstream port and the non-transparent port of PEX 8618 allowing the system to be reconfigured ...

Page 4

... Description 16 Lane, 16 Port PCIe Switch, 324-ball HSBGA 19x19mm 16 Lane, 16 Port PCIe Switch, 324-ball HSBGA 19x19mm PEX 8618 Rapid Development Kit – Base Board with x4 Upstream and 12 x1 Downstream PEX 8618 Rapid Development Kit – Base Board with x8 Upstream and Eight x1 Downstream PEX 8618 Rapid Development Kit – ...

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