874001AGI-05LF Integrated Device Technology (Idt), 874001AGI-05LF Datasheet
![no-image](/images/manufacturer_photos/0/3/333/integrated_device_technology__idt__sml.jpg)
874001AGI-05LF
Specifications of 874001AGI-05LF
Related parts for 874001AGI-05LF
874001AGI-05LF Summary of contents
Page 1
... Phase nCLK Detector Pulldown MR 2 Pullup/Pulldown F_SEL[1:0] Pullup OE ICS874001AGI-05 REVISION A JANUARY 14, 2011 Features • One differential LVDS output pair • One differential clock input • CLK, nCLK supports the following input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Input frequency range: 98MHz to 128MHz • ...
Page 2
... IN R Input Pullup Resistor PULLUP R Input Pulldown Resistor PULLDOWN ICS874001AGI-05 REVISION A JANUARY 14, 2011 Type Description PLL select pin. When LOW, bypasses the PLL. When HIGH selects the PLL. Pullup LVCMOS/LVTTL interface levels. See Table 3B. No connect. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output LOW and the inverted output HIGH ...
Page 3
... Bypass 1 VCO (default) Table 3C. F_SELx Function Table Inputs F_SEL1 F_SEL0 Output Divider ICS874001AGI-05 REVISION A JANUARY 14, 2011 Output Frequency (MHz) ÷ 128 ÷4 122.5 - 160 ÷2 245 - 320 (default) ÷1 490 - 640 3 PCI EXPRESS™ JITTER ATTENUATOR ©2011 Integrated Device Technology, Inc. ...
Page 4
... Input High Voltage IH V Input Low Voltage IL PLL_SEL, F_SEL1 Input High Current IH F_SEL0, MR PLL_SEL, F_SEL1 Input Low Current IL F_SEL0, MR ICS874001AGI-05 REVISION A JANUARY 14, 2011 Rating 4.6V -0. 0.5V DD 10mA 15mA 86.7°C/W (0 mps) -65°C to 150° 3.3V ± 0.3V -40°C to 85°C DD DDO A Test Conditions ...
Page 5
... IL NOTE 2: Common mode input voltage is defined as V Table 4D. LVDS DC Characteristics, V Symbol Parameter V Differential Output Voltage OD ∆V V Magnitude Change Offset Voltage OS ∆V V Magnitude Change OS OS ICS874001AGI-05 REVISION A JANUARY 14, 2011 = V = 3.3V ± 0.3V DDO A Test Conditions 3. 3. 3.6V ...
Page 6
... Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t (High Band) and 3.0ps RMS for t REFCLK_LF_RMS NOTE 4: Guaranteed only when input clock source is PCI Express and PCI Express Gen 2 compliant. ICS874001AGI-05 REVISION A JANUARY 14, 2011 = V = 3.3V ± 0.3V -40°C to 85°C ...
Page 7
... LVDS Output Load AC Test Circuit PERIOD t PW odc = t PERIOD Output Duty Cycle/Pulse Width/Period nQ 80% 20 Output Rise/Fall Time ICS874001AGI-05 REVISION A JANUARY 14, 2011 SCOPE Qx LVDS nQx Differential Input Level x 100% Cycle-to-Cycle Jitter 80 Input 20 Offset Voltage Setup 7 PCI EXPRESS™ JITTER ATTENUATOR V DD nCLK ...
Page 8
... Applications Information Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS874001AGI-05 REVISION A JANUARY 14, 2011 out ➤ 100 V /∆ ➤ ...
Page 9
... This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS874001AGI-05 REVISION A JANUARY 14, 2011 line impedance. For most 50Ω applications, R3 and R4 can be 100Ω ...
Page 10
... HCSL R1 50Ω *Optional – R3 and R4 can be 0Ω Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS874001AGI-05 REVISION A JANUARY 14, 2011 vendor of the driver component to confirm the driver termination and V requirements. For example, in Figure 2A, the input termination PP CMR applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation ...
Page 11
... The standard LVDS Driver 100Ω Differential Transmission Line Figure 3. Typical LVDS Driver Termination ICS874001AGI-05 REVISION A JANUARY 14, 2011 termination schematic as shown in Figure 3 can be used with either type of output structure. If using a non-standard termination recommended to contact IDT and confirm if the output is a current source or a voltage source type structure ...
Page 12
... PCIe Gen 1 Magnitude of Transfer Function ICS874001AGI-05 REVISION A JANUARY 14, 2011 For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – ...
Page 13
... VDD Ferrite Bead C7 C6 0.1uF 10uF Figure 4. ICS874001I-05 Schematic Layout ICS874001AGI-05 REVISION A JANUARY 14, 2011 Power supply filter recommendations are a general guideline 3.3V. used for reducing external noise from coupling into the devices. The DD DDA DDO filter performance is designed for wide range of noise frequencies. ...
Page 14
... This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). θ Table 6. Thermal Resistance JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS874001AGI-05 REVISION A JANUARY 14, 2011 = 3.3V + 0.3V = 3.6V, which gives worst case results 3.6V * (75mA + 13mA) = 316.8mW DD_MAX ...
Page 15
... Air Flow Table for a 20 Lead TSSOP JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS874001I-05 is: 1,608 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP ICS874001AGI-05 REVISION A JANUARY 14, 2011 θ by Velocity 86.7°C/W 82.4°C/W ...
Page 16
... Marking 874001AGI-05LF ICS4001AI05L 874001AGI-05LFT ICS4001AI05L NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...
Page 17
... Updated Wiring the Differential Input to Accept Single-ended Levels application note. 11 Updated LVDS Driver Termination application note Update PCI Express Application Note. 13 Updated Schematic Layout application Note and diagram. Converted datasheet format. ICS874001AGI-05 REVISION A JANUARY 14, 2011 PCI EXPRESS™ JITTER ATTENUATOR 17 ©2011 Integrated Device Technology, Inc. Date 1/14/11 ...
Page 18
ICS74001I-05 Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to ...