PM7543FSZ Analog Devices Inc, PM7543FSZ Datasheet - Page 10

• Manufacturer Part Number: PM7543FSZ
• Description: DAC 1-CH R-2R 12-Bit 16-Pin SOIC
• Manufacturer: Analog Devices Inc

Specifications of PM7543FSZ

• Package: 16SOIC
• Resolution: 12 Bit
• Architecture: R-2R
• Digital Interface Type: Serial
• Number Of Outputs Per Chip: 1
• Output Type: Current
• Full Scale Error: ±2 LSB
• Integral Nonlinearity Error: ±1 LSB
• Settling Time: 1µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

on
approximately-VREF
code.
In many
very
ponents
TABLE
---
_____n__"
UNIPOLAR OPERATION
The circuitshown
reference
put is shown
input
FIGURE 7: Unipolar Operation with High Accuracy Op Amp (2-
Quadrant)
NOTES:
1- CLR
PM-7543
Input Register
5TB4
ANALOG
S
circuit performance.
ellee! on Input Register.
--
X
X
X
0
0
0
1
CONTROl.
low gain
voltage
The
INPUTS:
SERIAl
INPUT
~
-10V
DATA
VA"
CLR
1: PM-7543
applications
0 Asynchronously resets DACRegisterto 00000000 0000,but has no
(R1
voltage. The
relationship
DEVICES fAX-ON-DEnAND HOTLINE
5TB3
1-
and
error permit
1
X
X
X
I
.
0
in Table
range
1
1
1
the
in Figures 7 and 8 may
of the op
Control Inputs
Truth Table
the
external
5TB2 STB1
=
(4095/4096)
2. The
S
between
-'-5V
X
X
0
0
X
0
1
circuit'soutput willrange
PM-
the elimination
(2-aUADRANT)
PM-7543 logic Inputs
amp
7543's
V REF voltage range
RFEEDBACK)
S
the digital input and
X
X
X
0
0
0
or :t25V.
depending
negligible
DAC Register
of the trimming
be used with an AC
without
whichever
CLR
X
X
X
X
0
upon the digitalinput
zero scale
-
-ISV
Page 23
between
is the maximum
adverse
the
is lowest.
of the com-
analog
Control Inputs
lD2
error and
X
X
X
X
X
X
0
1
QV and
effects
Vour
or DC
out-
-10-
lD1
X
X
X
X
X
X
1
0
01
0000
0000
2.
TABLE
MSB
NOTES:
forthe top grade part, or 0.048%
2- Serial data is loaded into Input Register MS8 lI'st, on edges shown .f IS
3- 0 = Logic LOW. 1 = Logie HIGH, X= Don'tCare-
1000
1000
1. Nominal f ull s cale forthecircuits01Figures7 and 8 is givenby
in Figure
1 1 1 1
For applications requiring a tighter gain error than
Nominal LSB magnitude
LSB
FS =-VREF
positive edge. 1. is negative edge.
1 1
Reset
(Code:
(Asynchronous
of Input Register
Serial Data Bit Loaded
intoInputRegister
No Operation
No Operation
Load
=
DIGITAL
VREF
2: UnipolarCode
8 may
DAC
DAC
0000
0000
0000
0000
0000
1 1 1 1
1 1 1 1
{
(
-1---
4095
4096
4096
PM-7543 Operation
be
Register
Register to Zero Code
INPUT
}
)
0000
-
or VREF (2--<1)
used.
(Input Register)
(DAC
Operation)
for !he drcuits
0000)
0000
0000
000
000
1 1 1 1
1 1 1 1
Gain
Register)
with the Contents
Table
lSB
from SRI
-
error may
1
1
for the lower grade
01 Figures
NOMINALANALOG OUTPUT
---------
-VAEF (~~~~)
-v REF
-VREF(~~~~) =
-v
-v
-v
REF
REF
REF
be trimmed
in Figures 7 and 8)
(VOUT as shown
7 and 8 is given by
------------------
(
(
bo1-6)
(40~6) = 0
204~"
4096
201I
4096
------
__nn___-
)
)
0_024%
by adjusting
part,
~
-----
the circuit
----
REV.D
at25"C
Notes
2.3
1,3
R1
3
3
3
-