AD7398BRU Analog Devices Inc, AD7398BRU Datasheet - Page 5

• Manufacturer Part Number: AD7398BRU
• Description: DAC 4-CH R-2R 12-Bit 16-Pin TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7398BRU

• Package: 16TSSOP
• Resolution: 12 Bit
• Conversion Rate: 167 KSPS
• Architecture: R-2R
• Digital Interface Type: Serial (3-Wire, SPI)
• Number Of Outputs Per Chip: 4
• Output Type: Voltage
• Full Scale Error: ±2.5 mV
• Integral Nonlinearity Error: ±1.5 LSB
• Maximum Settling Time: 6(Typ) us
• Rohs Status: RoHS non-compliant
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 16mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP

Parameter
AC CHARACTERISTICS
SUPPLY CHARACTERISTICS
1
2
3
4
5
6
7
8
TIMING DIAGRAMS
One LSB = V
The first two codes (000
These parameters are guaranteed by design and not subject to production testing.
When V
voltage of the output buffer, which is the same as the V
Input resistance is code dependent.
Typicals represent average readings measured at 25°C.
All input control signals are specified with t
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Output Slew Rate
Settling Time
Shutdown Recovery
DAC Glitch
Digital Feedthrough
Feedthrough
Shutdown Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
REF
is connected to either the V
REF
LDAC
LDAC
/1024 V for the 10-bit AD7399.
CLK
CLK
SDI
CS
CS
8
H
and 001
t
SA
CSS
t
LDS
t
H
t
LDS
) are excluded from the linearity error measurement in single-supply operation.
CSS
SD
DD
Symbol
SR
t
t
Q
Q
V
I
I
I
I
P
PSS
DD_SD
DD
DD
SS
or the V
S
SDR
OUT
DISS
DF
R
A1
/V
= t
REF
t
F
CH
SS
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Figure 3. AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only)
power supply, the corresponding V
A0
ZSE
D11
error specification. See additional discussion in the Theory of Operation section.
Condition
Data = 000
To ±0.1% of full scale
Code 1FF
V
No load
V
V
V
ΔV
V
Figure 4. Continuous Clock Timing Diagram
REF
IL
IL
IL
t
IL
t
CL
DS
data = 000
−40°C < T
−40°C < T
= 0 V, no load,
= 0 V, no load
= 0 V, no load
DD
= 0 V, no load,
D10
= 1.5 V
= ±5%
H
D9
t
H
to 200
DC
DH
Rev. C | Page 5 of 24
to 3FF
A
A
+ 1 V p-p,
H
< +125°C
< +85°C
, f = 100 kHz
D8
H
H
to 1FF
to 000
D7
t
OUT
CH
voltage programs between ground and the supply voltage minus the offset
H
t
CSH
H
D6
t
CL
D5
t
LDH
3 V to 5 V ± 10%
2
6
6
150
15
−63
30/60
1.5/2.8
1.5/2.6
1.5/2.5
5
0.006
D4
1/
t
f
t
LDAC
D3
CLK
CSS
D2
t
LDS
t
D1
CSH
±5 V ± 10%
2
6
6
150
15
−63
30/60
1.6/3
1.6/2.8
1.6/2.7
16
0.006
t
LDH
D0
AD7398/AD7399
t
LDAC
IN
REG
LD
Unit
V/μs typ
μs typ
μs typ
nVs typ
nVs typ
dB typ
μA typ/max
mA typ/max
mA typ/max
mA typ/max
mW typ
%/% max