AD557JNZ Analog Devices Inc, AD557JNZ Datasheet - Page 4

• Manufacturer Part Number: AD557JNZ
• Description: DAC 1-CH R-2R 8-Bit 16-Pin PDIP
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD557JNZ

• Package: 16PDIP
• Resolution: 8 Bit
• Conversion Rate: 1.25 MSPS
• Architecture: R-2R
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Integral Nonlinearity Error: 1 LSB
• Maximum Settling Time: 1.5 us
• Settling Time: 800ns
• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 125mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Resolution (bits): 8bit
• Sampling Rate: 1.25MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Supply Current: 15mA
• Digital Ic Case Style: DIP
• No. Of Pins: 16
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD557
APPLICATIONS
Grounding and Bypassing
All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the AD557 is intended for application in microcom-
puter systems where digital noise is prevalent, special care must
be taken to assure that its inherent precision is realized.
The AD557 has two ground (common) pins; this minimizes
ground drops and noise in the analog signal path. Figure 4
shows how the ground connections should be made.
It is often advisable to maintain separate analog and digital
grounds throughout a complete system, tying them common in
one place only. If the common tie-point is remote and acciden-
tal disconnection of that one common tie-point occurs due to
card removal with power on, a large differential voltage between
the two commons could develop. To protect devices that inter-
face to both digital and analog parts of the system, such as the
AD557, it is recommended that common ground tie-points
should be provided at each such device. If only one system
ground can be connected directly to the AD557, it is recom-
mended that analog common be selected.
Using a “False” Ground
Many applications, such as disk drives, require servo control
voltages that swing on either side of a “false” ground. This
ground is usually created by dividing the 12 V supply equally
and calling the midpoint voltage “ground.”
Figure 5 shows an easy and inexpensive way to implement this.
The AD586 is used to provide a stable 5 V reference from the
system’s 12 V supply. The op amp shown likewise operates from
a single (12 V) supply available in the system. The resulting out-
put at the V
of 5 V. AD557 input code vs. V
OUTPUT
AMP
AD557
OUT
node is ± 2.5 V around the “false” ground point
16
15
14
13
12
11
V
V
V
GND
GND
+V
100k
OUT
OUT
OUT
CC
100k
SENSE A
SENSE B
OUT
0.1 F
200k
100k
is shown in Figure 6.
GROUND
“FALSE”
1/4 LM324
5V
6
AD586
TO SYSTEM GND
TO SYSTEM GND
(SEE TEXT)
TO SYSTEM V
R
L
4
2
V
IN
V
12V
OUT
CC
Timing and Control
The AD557 has data input latches that simplify interface to 8-
and 16-bit data buses. These latches are controlled by Chip
Enable (CE) and Chip Select (CS) inputs. CE and CS are inter-
nally “NORed” so that the latches transmit input data to the
DAC section when both CE and CS are at Logic “0.” If the
application does not involve a data bus, a “00” condition allows
for direct operation of the DAC. When either CE or CS go to
Logic “1,” the input data is latched into the registers and held
until both CE and CS return to “0.” (Unused CE or CS inputs
should be tied to ground.) The truth table is given in Table I.
The logic function is also shown in Figure 6.
Input Data
0
1
0
1
0
1
X
X
NOTES
X = Does not matter
g
In a level-triggered latch such as that used in the AD557, there
is an interaction between the data setup and hold times and
the width of the enable pulse. In an effort to reduce the time
required to test all possible combinations in production, the
AD557 is tested with t
T
comply with these specifications may result in data not being
latched properly.
Figure 7 shows the timing for the data and control signals, CE
and CS are identical in timing as well as in function.
= Logic Threshold at Positive-Going Transition
MIN
and T
Table I. AD557 Control Logic Truth Table
MAX
V OUTPUT
CS OR CE
INPUTS
CE
0
0
g
g
0
0
1
X
, with t
t
t
t
t
W
DH
DS
SETTLING
DATA
DAC
= STROBE PULSEWIDTH = 225ns min
= DATA HOLD TIME = 10ns min
= DATA SETUP TIME = 225ns min
7.5
5.0
2.5
V
00H
0.8V
0.8V
DS
DH
OUT
= DAC SETTLING TIME TO
AD557 INPUT CODE
= t
= 10 ns at all temperatures. Failure to
CS
0
0
0
0
g
g
X
1
W
80H
= 225 ns at 25°C and 300 ns at
t
SETTLING
t
t
W
DS
DAC Data
0
1
0
1
0
1
Previous Data
Previous Data
FFH
1/2 LSB
t
1/2 LSB
DH
2.0V
2.0V
Latch
Condition
“Transparent”
“Transparent”
Latching
Latching
Latching
Latching
Latched
Latched