PRIXP422ABB Intel, PRIXP422ABB Datasheet - Page 41

• Manufacturer Part Number: PRIXP422ABB
• Description: Network Proc 1.3V/3.3V 266MHz 492-Pin BGA
• Manufacturer: Intel

Specifications of PRIXP422ABB

• Package: 492BGA
• Core Operating Frequency: 266 MHz
• Operating Supply Voltage: 1.3|3.3 V
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Functional Signal Descriptions
Table 12.
Table 13.
June 2007
41
UTOPIA Level 2 Interface (Sheet 2 of 2)
Expansion Bus Interface (Sheet 1 of 2)
UTP_IP_SOC
UTP_IP_DATA[7:0]
UTP_IP_ADDR[4:0]
UTP_IP_FCO
†
††
EX_CLK
EX_ALE
EX_ADDR[23:0]
EX_WR_N
†
††
Name
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs
that have this signal pulled low.
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs
that have this signal pulled low.
Power
or Sys
Reset
Reset
Z
Z
H
Z
Power
or Sys
Reset
Reset
Z
Z
Z
Z
Reset
Post
Z
0
H
1
Reset
Post
VI
VI
VI
Z
Type
I/O
O
O
I
Type
†
I/O
O
Table 5 on page
Table 5 on page
I
I
Input clock signal used to sample all expansion interface inputs and clock all expansion interface outputs.
Address-latch enable used for multiplexed address/data bus accesses. Used in Intel and Motorola* multiplexed
modes of operation.
Expansion-bus address used as an output for data accesses over the expansion bus. Also, used as an input
during reset to capture device configuration. These signals have a weak pull-up resistor attached internally.
Based on the desired configuration, various address signals must be pulled low in order for the device to operate
in the desired mode.
Intel-mode write strobe / Motorola-mode data strobe (EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N).
†
Start of Cell. RX_SOC
Active-high signal that is asserted when UTP_IP_DATA contains the first valid byte of a transmitted cell.
Should be pulled high
UTOPIA input data. Also known as RX_DATA.
Used by to the processor to receive data from an ATM UTOPIA-Level-2-compliant PHY.
Should be pulled high
Receive PHY address bus.
Used by the processor when operating in MPHY mode to poll and select a single PHY at any one given time.
UTOPIA Input Data Flow Control Output signal: Also known as the RX_ENB_N.
In SPHY configurations, UTP_IP_FCO is used to inform the PHY that the processor is ready to accept data.
In MPHY configurations, UTP_IP_FCO is used to select which PHY will drive the UTP_RX_DATA and
UTP_RX_SOC signals. The PHY is selected by placing the PHY’s address on the UTP_IP_ADDR and bringing
UTP_OP_FCO to logic 1 during the current clock, followed by the UTP_OP_FCO going to a logic 0 on the next
clock cycle.
30.
30.
††
††
through a 10-KΩ resistor when not being utilized in the system.
through a 10-KΩ resistor when not being utilized in the system.
Intel
®
IXP45X and Intel
Description
Description
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
252479-007US