ZL30106QDG Zarlink, ZL30106QDG Datasheet - Page 13

• Manufacturer Part Number: ZL30106QDG
• Description: SONET/SDH/PDH Network Interface 64-Pin TQFP
• Manufacturer: Zarlink

Specifications of ZL30106QDG

• Package: 64TQFP
• Power Supply Type: Analog
• Typical Supply Current: 68(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.62 V
• Maximum Operating Supply Voltage: 3.63 V

3.2
The input references are monitored by three independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the
reference input signal when the failures are present for more than 50 ms. The single cycle and coarse frequency
failures must be absent for 200 ms to let the timer re-qualify the input reference signal as valid. Multiple failures of
less than 50 ms each have an accumulative effect and will disqualify the reference eventually. This is illustrated in
Figure 4 where REF0 experiences disruptions while REF1 is stable.
REF0 /
REF1 /
REF2
•
•
•
•
Reference Monitor
Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference
clock is 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz and provides this
information to the various monitor circuits and the phase detector circuit of the DPLL.
Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock
is within the selected accuracy range, see Table 1.
Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of
approximately 30 μs to quickly detect large frequency changes.
Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large
phase hits or the complete loss of the clock.
Reference Frequency
Precise Frequency
Coarse Frequency
Single Cycle
Detector
Monitor
Monitor
Monitor
Figure 3 - Reference Monitor Circuit
OR
Zarlink Semiconductor Inc.
ZL30106
REF_OOR = reference out of range.
REF_DIS= reference disrupted.
Both are internal signals.
dis/re-qualify
13
timer
OR
OR
REF_OOR
REF_DIS
Mode select
state machine
Reference
select
state machine
Data Sheet
REF_SEL1:0
HOLDOVER
REF_FAIL0 /
REF_FAIL1 /
REF_FAIL2