SI3200-G-GS Silicon Laboratories Inc, SI3200-G-GS Datasheet - Page 11
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI3200-G-GS
Manufacturer Part Number
SI3200-G-GS
Description
SLIC 2-CH 63dB 45mA 3.3V 6-Pin SMD
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Specifications of SI3200-G-GS
Package
6SMD
Number Of Channels Per Chip
2
Polarity Reversal
Yes
Longitudinal Balanced
63 dB
Loop Current
45 mA
Minimum Operating Supply Voltage
3.13 V
Typical Operating Supply Voltage
3.3 V
Typical Supply Current
0.11 mA
Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
GCI, PCM, SPI
Number Of Circuits
2
Voltage - Supply
3.3V, 5V
Current - Supply
110µA
Power (watts)
941mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Includes
Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI3200-G-GS
Manufacturer:
SiliconL
Quantity:
48
Company:
Part Number:
SI3200-G-GS
Manufacturer:
Genesis
Quantity:
510
Company:
Part Number:
SI3200-G-GSR
Manufacturer:
SILICON
Quantity:
12 000
Table 5. AC Characteristics
(V
Parameter
Overload Level
Overload Compression
Single Frequency Distortion
Signal-to-(Noise + Distortion)
Ratio
Audio Tone Generator Signal-to-
Distortion Ratio
Intermodulation Distortion
Gain Accuracy
Attenuation Distortion vs. Freq.
Group Delay vs. Frequency
Gain Tracking
Round-Trip Group Delay
Crosstalk between Channels
TX or RX to TX
TX or RX to RX
Gain Step Increment
2-Wire Return Loss
Transhybrid Balance
Notes:
DD
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
2. Analog signal measured as V
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the
5. V
6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-
, V
2
DD1
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
complete range. See "3.25. Audio Path Processing" on page 70.
coefficients.
hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
DD1
– V
– V
DD4
3
DD4
2
2
=
=
3.13 to 5.25 V, T
5
3.3 V, V
4
5
BAT
1
=
TIP
–52 V, no fuse resistors, R
A
= 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
– V
Active off-hook, and OHT, any Z
2-Wire to PCM or PCM to 2-Wire
2-Wire – PCM or PCM – 2-Wire:
1014 Hz, Within same time-slot
0 dBm0, Active off-hook, and
RING
1014 Hz, Any gain setting
reference level –10 dBm
PCM – 2-Wire – PCM:
Step size around 0 dB
. Assumes ideal line impedance matching.
1014 Hz sine wave,
16-bit Linear mode
200 Hz to 3.4 kHz
200 Hz – 3.4 kHz,
200 Hz to 3.4 kHz
300 Hz to 3.4 kHz
300 Hz to 3.4 kHz
200 Hz to 3.4 kHz
300 Hz to 3.4 kHz
–37 dB to –50 dB
–50 dB to –60 dB
D/A or A/D 8-bit
Test Condition
TX/RX Performance
3 dB to –37 dB
2-Wire – PCM
OHT, any Z
Signal level:
0 dBm 0
0 dBm0,
Rev. 1.3
L
=
T
600 Ω, Z
Si3220/25 Si3200/02
S
T
=
600 Ω synthesized using RS register
Figure 7,8
Figure 6
Figure 5
Figure 9
–0.25
Min
2.5
46
26
34
—
—
—
—
—
—
—
—
—
—
—
±0.0005
–108
–108
Typ
–85
–87
600
30
40
—
—
—
—
—
—
—
—
—
—
—
—
± 0.25
+0.25
± 0.5
± 1.0
Max
–65
–65
–41
700
–75
–75
—
—
—
—
—
—
—
—
—
—
Unit
V
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
µs
—
—
—
PK
11