SI3200-G-GS Silicon Laboratories Inc, SI3200-G-GS Datasheet - Page 108

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SI3200-G-GS

Manufacturer Part Number
SI3200-G-GS
Description
SLIC 2-CH 63dB 45mA 3.3V 6-Pin SMD
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheets

Specifications of SI3200-G-GS

Package
6SMD
Number Of Channels Per Chip
2
Polarity Reversal
Yes
Longitudinal Balanced
63 dB
Loop Current
45 mA
Minimum Operating Supply Voltage
3.13 V
Typical Operating Supply Voltage
3.3 V
Typical Supply Current
0.11 mA
Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
GCI, PCM, SPI
Number Of Circuits
2
Voltage - Supply
3.3V, 5V
Current - Supply
110µA
Power (watts)
941mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Includes
Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Si3232
PTH34: Q3/Q4 Power Alarm Threshold (RAM Address 38)
Reset settings = 0x00
PTH56: Q5/Q6 Power Alarm Threshold (RAM Address 39)
Reset settings = 0x00
RB56: Q5/Q6 Base Resistance (RAM Address 43)
Reset settings = 0x00
108
15:0
15:0
15:0
Name
Name
Name
Type
Type
Type
Bit
Bit
Bit
Bit
Bit
Bit
D15
D15
D15
PTH34[15:0]
PTH56[15:0]
RB56[15:0]
Name
Name
Name
D14
D14
D14
D13
D13
D13
Q3/Q4 Power Alarm Threshold.
Programs the power threshold in transistors Q3 and Q4 at which a power alarm is
triggered. 0 to 1.03 W programmable range, 31.4 µ W/LSB. Refer to "4.4.6. Power
Filter and Alarms" on page 27 for use.
Q5/Q6 Power Alarm Threshold.
Programs the power threshold in transistors Q5 and Q6 at which a power alarm is
triggered. 0 to 16.319 W programmable range, 498 µ W/LSB. Refer to "4.4.6. Power
Filter and Alarms" on page 27 for use.
Q5/Q6 Base Resistance.
Programs the base resistance feeding transistors, Q5 and Q6.
D12
D12
D12
D11
D11
D11
D10
D10
D10
Preliminary Rev. 0.96
D9
D9
D9
PTH34[15:0]
PTH56[15:0]
RB56[15:0]
D8
D8
D8
R/W
R/W
R/W
D7
D7
D7
Function
Function
Function
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0

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