MT88L70AN1 Zarlink, MT88L70AN1 Datasheet - Page 2

• Manufacturer Part Number: MT88L70AN1
• Description: DTMF RX 3.58MHz CMOS 3V 20-Pin SSOP Tube
• Manufacturer: Zarlink

Specifications of MT88L70AN1

• Package: 20SSOP
• Operating Frequency: 3.58 MHz
• Typical Supply Current: 2 mA
• Typical Operating Supply Voltage: 3 V
• Minimum Operating Supply Voltage: 2.7 V
• Maximum Operating Supply Voltage: 3.6 V

Pin Description
11-
18
10
14
15
16
1
2
3
4
5
6
7
8
9
Pin #
12-
20
10
15
17
18
11
1
2
3
4
5
6
8
9
PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the
Name
OSC1 Clock (Input).
OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
TOE
V
INH
V
StD
IN+
ESt
GS
IN-
Ref
SS
PWDN
OSC2
OSC1
VRef
VSS
INH
Non-Inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage (Output). Nominally V
and Figure 6).
Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and
D. This pin input is internally pulled down.
pin input is internally pulled down.
completes the internal oscillator circuit.
Ground (Input). 0 V typical.
Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled
up internally.
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
IN+
GS
IN-
18 PIN PDIP/SOIC
1
2
3
4
5
6
7
8
9
TSt
.
18
17
16
15
14
13
12
11
10
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
Figure 2 - Pin Connections
Zarlink Semiconductor Inc.
MT88L70
2
Description
DD
/2 is used to bias inputs at mid-rail (see Figure 5
PWDN
OSC1
OSC2
VRef
VSS
INH
IN+
GS
NC
IN-
10
1
2
3
4
5
6
7
8
9
20 PIN SSOP
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
NC
Data Sheet