TDA8754HL11BE-T NXP Semiconductors, TDA8754HL11BE-T Datasheet - Page 14

• Manufacturer Part Number: TDA8754HL11BE-T
• Description: Video ICs 3X8 BIT VIDEO A/D-110 MSPS
• Manufacturer: NXP Semiconductors

Specifications of TDA8754HL11BE-T

• Package / Case: SOT-486
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: TDA8754HL/11/C1,51

Philips Semiconductors
9397 750 14984
Product data sheet
8.1.1.2 Power-down mode
8.2.1 Analog multiplexers
8.2.2 Activity detection
8.2.3 ADC
8.2 Analog video input
In Power-down mode the status of the blocks is as follows:
The RGB/YUV video inputs are externally AC coupled and are internally DC polarized.
The synchronization signals are also used by the device as input for the internal PLL and
the automatic clamp.
The TDA8754 has two analog inputs (RGB input 1 and RGB input 2) selectable via the
I
The sync management can be achieved in several ways:
When a signal is connected or disconnected on pins HSYNC1(2), CHSYNC1(2),
VSYNC1(2) and SOG1(2), then bit HPDO is set to logic 1 and pin HPDO is set to HIGH to
advise the user of a change. Bit HPDO is set to logic 0 and pin HPDO is set to LOW when
register ACTIVITY2 has been read.
When the synchronization pulse on pin SOG is 3-level, the system will automatically be
able to detect that a 3-level sync is present and will force bit 3LEVEL to logic 1. It is
possible to disable this function with bit FTRILEVEL.
When an interlaced signal is detected, bit ACFIELD is set to logic 1. When the signal
detected is progressive, this bit is set to logic 0. Any change in this bit results into setting
bit HPDO = 1 and pin HPDO = HIGH.
A field detection unit is available on pin FIELDO which output is given by the sync
separator. The field identity is given by pin FIELDO. This pin gives the field of interlaced
signal input.
An automatic polarity detection is also available on pins HSYNC1(2), VSYNC1(2) and
CHSYNC1(2). The output on pin HPDO is not affected by the change of polarity of these
inputs.
The three ADCs are designed to convert R, G and B (or Y, U and V) signals at a
maximum frequency of 270 Msample/s. The ADC input range is 1 V (p-p) full-scale and
the pipeline delay is 2 ADC clock cycles from the input sampling to the data output.
2
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•
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C-bus.
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•
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All digital inputs and outputs are in high-impedance state
All blocks are inactive (I
Analog output is left uncontrolled
I
Choice between two analog inputs HSYNC and two analog inputs VSYNC
Choice between two analog inputs CHSYNC
Choice between two analog inputs SOG.
2
C-bus is left in high-impedance state.
Rev. 06 — 16 June 2005
2
C-bus, activity detection, ADCs, etc.)
Triple 8-bit video ADC up to 270 Msps
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
TDA8754
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