DS1846E-010 Maxim Integrated Products, DS1846E-010 Datasheet - Page 7

• Manufacturer Part Number: DS1846E-010
• Description: Digital Potentiometer ICs
• Manufacturer: Maxim Integrated Products

Specifications of DS1846E-010

• Number Of Pots: Triple
• Taps Per Pot: 100, 256
• Resistance: 10 KOhms, 100 KOhms
• Wiper Memory: Non Volatile
• Digital Interface: Serial (2-Wire)
• Operating Supply Voltage: 5 V
• Supply Current: 200 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Package / Case: TSSOP-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS1846
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bidirectional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the start and stop conditions. The DS1846 operates as a
slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL.
The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. Timing diagrams for the
2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is
provided in the AC ELECTRICAL CHARACTERISTICS table for 2-wire serial communications.
The following bus protocol has been defined:
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data line from high to low while the clock is high
defines a start condition.
Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high
defines the stop condition.
Data Valid: The state of the data line represents valid data when, after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line can be changed during
the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how
data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of
data bytes transferred between start and stop conditions is not limited and is determined by the master
device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)
are defined. The DS1846 works in both modes.
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