DS1856E-050 Maxim Integrated Products, DS1856E-050 Datasheet - Page 30

• Manufacturer Part Number: DS1856E-050
• Description: Digital Potentiometer ICs
• Manufacturer: Maxim Integrated Products

Specifications of DS1856E-050

• Number Of Pots: Dual
• Taps Per Pot: 256
• Resistance: 50 KOhms
• Wiper Memory: Non Volatile
• Digital Interface: Serial (2-Wire)
• Operating Supply Voltage: 3.3 V, 5 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.85 V
• Package / Case: TSSOP-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
30
Within the bus specifications, a standard mode
(100kHz clock rate) and a fast mode (400kHz clock
rate) are defined. The DS1856 works in both modes.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an acknowledge after the byte has
been received. The master device must generate an
extra clock pulse, which is associated with this acknowl-
edge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that
the SDA line is a stable low during the high period of the
acknowledge-related clock pulse. Setup and hold times
must be taken into account. A master must signal an end
of data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
1)
2)
Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the command/control byte. Next follows
a number of data bytes. The slave returns an
acknowledge bit after each received byte.
Data transfer from a slave transmitter to a mas-
ter receiver. The master transmits the first byte
(the command/control byte) to the slave. The slave
then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to
the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At
the end of the last received byte, a not acknowl-
edge can be returned.
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The master device generates all serial clock pulses and
the START and STOP conditions. A transfer is ended with
a STOP condition or with a repeated START condition.
Since a repeated START condition is also the beginning
of the next serial transfer, the bus is not released.
The DS1856 can operate in the following two modes:
1)
2)
Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is trans-
mitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
Address recognition is performed by hardware
after the slave (device) address and direction bit
have been received.
Slave Transmitter Mode: The first byte is
received and handled as in the slave receiver
mode. However, in this mode the direction bit
indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the DS1856,
while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning
and end of a serial transfer.