LAN9117-MD SMSC, LAN9117-MD Datasheet - Page 20

• Manufacturer Part Number: LAN9117-MD
• Description: Ethernet ICs HiPerfrm Sngl-Chip 10/100 Ethrnt
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9117-MD

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.5 (07-11-08)
36, 37,
24, 23,
38, 39
22, 75
NO.
PIN
40
21
26
25
33
32
29
30
Transmit Data [3:0]
Management Data
Receive Data[3:0]
Transmit Enable
IO/External PHY
Collision Detect:
Transmit Clock:
Receive Clock
Receive Error
Carrier Sense
Receive Data
NAME
Detect
Valid:
(EXT_PHY_DET)
SYMBOL
TXD[3:0]
RXD[3:0]
RX_CLK
TX_CLK
RX_ER
RX_DV
TX_EN
MDIO
COL/
CRS
Table 2.6 MII Interface Signals
DATASHEET
BUFFER
O8 (PD)
O8 (PD)
I (PD)
I (PD)
I (PD)
I (PD)
I (PD)
I (PD)
I (PD)
TYPE
(PD)
I/O8
20
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
NUM
PINS
1
4
1
1
1
1
1
1
1
1
Transmit Clock: 25MHz in 100Base-
TX mode. 2.5MHz in 10Base-T
mode.
Transmit Data 3-0: Data bits that are
accepted by the PHY for
transmission.
When the internal PHY is selected,
these signals are driven low (0).
Transmit Enable: Indicates that valid
data is presented on the TXD[3:0]
signals, for transmission.
When the internal PHY is selected,
this signal is driven low (0).
Receive Clock: 25MHz in 100Base-
TX mode. 2.5MHz in 10Base-T
mode.
Receive Error: Asserted bt the PHY
to indicate that an error was detected
somewhere in the frame presently
being transferred from the PHY.
MII Collision Detect: Asserted by the
PHY to indicate detection of collision
condition.
Receive Data 3-0: Data bits that are
sent from the PHY to the Ethernet
MAC.
Carrier Sense: Indicates detection of
carrier.
Receive Data Valid: Indicates that
recovered and decoded data nibbles
are being presented by the PHY on
RXD[3:0].
Management Data IO: When
SMI_SEL = 1, this pin is the MII SMI
serial IO bus pin.
External PHY Detect: This pin also
functions as a strap input, which can
be used to indicate the presence of
an external PHY.
See
Note:
Note
See
"HW_CFG—Hardware
Configuration Register"
more information on
SMI_SEL and
EXT_PHY_DET
2.2.
DESCRIPTION
Section 5.3.9,
SMSC LAN9117
Datasheet
for