LAN91C110TQFP SMSC, LAN91C110TQFP Datasheet
LAN91C110TQFP
Specifications of LAN91C110TQFP
Related parts for LAN91C110TQFP
LAN91C110TQFP Summary of contents
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... Various CPU System Interfaces Support for 16 and 8 Bit CPU Accesses Asynchronous Bus Interface 128 Kbyte External Memory LAN91C110-PU for 144 pin TQFP lead-free RoHS Compliant package SMSC LAN91C110 Rev. B LAN91C110 REV. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“ ...
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... Figure 5.8 – Interrupt Generation for Transmit, Receive, MMU.................................................................. 48 Figure 7.1 - Asynchronous Cycle - nADS=0 ............................................................................................... 51 Figure 7.2 - Asynchronous Cycle - USING nADS....................................................................................... 51 Figure 7.3 – Address Latching for All Modes .............................................................................................. 52 SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 3 DATASHEET Datasheet Revision 1 ...
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... Figure 7.5 - MII Interface............................................................................................................................. 55 Figure 8.1 - 144 Pin TQFP Package Outlines............................................................................................. 56 List of Tables Table 5.1 - Internal I/O Space Mapping........................................................................................................ 18 Table 8.1 – 144 Pin TQFP Package Parameters ....................................................................................... 56 SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 4 DATASHEET Datasheet ...
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... The MII interface allows the use of a wide range of MII compliant Physical Layer (PHY) devices to be used with the LAN91C110. The LAN91C110 also provides an interface to the two-line MII serial management protocol. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
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... RD4 28 GND 29 RD3 30 RD2 31 RD1 32 VDD 33 RD0 34 RD15 35 RD14 36 SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications LAN91C110 144 Pin TQFP Figure 2.1 – Pin Configuration Page 6 DATASHEET Datasheet 108 A9 A8 107 A7 106 A6 105 104 A5 A4 ...
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... Interrupt INTR0 132 nRead nRD Strobe 134 nWrite nWR Strobe SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications BUFFER DESCRIPTION TYPE I Input. Used by LAN91C110 for internal register selection. I Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. ...
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... MDO ment Data Output 137 Manage- MCLK ment Clock SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications BUFFER DESCRIPTION TYPE I/O4 with Bidirectional. Carries the local buffer memory pullups read and write data. Reads are always 32 bits wide ...
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... O4 O12 OD16 I/O4 I/ with pullup I with pulldown SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications BUFFER TYPE I with Input. Indicates a code error detected by PHY. pulldown Used by the LAN91C110 to discard the packet being received. The error indication reported for this event is the same as a bad CRC (Receive Status Word bit 13) ...
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... WR FIFO FIFO SYSTEM BUS ADDRESS ADDRESS CONTROL CONTROL DATA DATA RA SRAM 32kx8 SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ARBITER DIRECT MEMORY ACCESS MEMORY MANAGEMENT UNIT RAM 25 MHz Figure 3.1 - LAN91C110 Block Diagram LAN91C110 FEAST ...
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... The Arbiter is also responsible for controlling the nRWE0-nRWE3 lines as a function of the bytes being written. Read accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to the appropriate lanes as a function of the address. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 11 ...
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... LAN91C110 using TX25 rising edges. TXEN100 goes inactive at the end of the packet on the last nibble of the CRC. During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous to the LAN91C110’s clocks and will be synchronized internally to TX25. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 12 DATASHEET Datasheet Revision 1 ...
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... PHY management through the MII management interface is supported by the LAN91C110 by providing the means to drive a tri-statable data output, a clock, and reading an input. Timing and framing for each management command generated by the CPU. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 13 ...
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... Bus Interface Address Control Unit WR FIFO Data RD FIFO Figure 4.1 - LAN91C110 Internal Block Diagram with Data Path SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Control Control Control Arbiter MMU TX/RX DMA FIFO Pointer TX Data ...
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... BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications 2nd Byte ...
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... BYTE 5 ALGNERR - Frame had alignment error. When MII SEL=1 alignment error is set when BADCRC=1 and an odd number of nibbles was received between SFD and RX_DV going inactive. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ODD CRC ...
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... The odd byte can be accessed using address (offset + 1). Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications HASH VALUE 5-0 ...
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... Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be done if the Revision Control register indicates the device is the LAN91C110. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Table 5.1 - Internal I/O Space Mapping ...
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... Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C110 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
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... LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit frame. MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced. Cleared when TX_SUC is high at the end of the packet being sent. SMSC LAN91C110 Rev. B NAME TYPE READ ONLY ...
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... RX_ABORT - This bit is set if a receive frame was aborted due to length longer than 2K bytes. The frame will not be received. The bit is cleared by RESET or by the CPU writing it low. Reserved - Must be 0. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME ...
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... MEMORY SIZE - This register can be read to determine the total memory size. All memory related information is represented in 256 * M byte units, where the multiplier M is determined by the MCR upper byte. These register default to FFh, which should be interpreted as 256. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE ...
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... The Configuration Register holds bits that define the adapter configuration and are not expected to change during run- time. This register is part of the EEPROM saved setup. HIGH MII Reserved BYTE SELECT 1 0 LOW 1 Reserved BYTE 1 0 SMSC LAN91C110 Rev. B NAME TYPE Lower Byte - REGISTER READ/WRITE Upper Byte - READ ONLY MEMORY SIZE MULTIPLIER ...
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... LAN91C110‘s registers. The 64k I/O space is fully decoded by the LAN91C110 down location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros. The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). Reserved - Must be 0. SMSC LAN91C110 Rev. B TYPE READ/WRITE A13 ...
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... HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 BANK 1 OFFSET NAME A Reserved. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE READ/WRITE ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS 5 ...
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... TE ENABLE bit. TE ENABLE defaults low (disabled). Transmit Error is any condition that clears TXENA with TX_SUC staying low as described in the EPHSR register. Reserved 2-0: These reserved bits must always be written to as zero(0). SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TYPE ...
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... The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME ...
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... Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence: SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
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... Note: For software compatibility with future versions, the value read from each FIFO register is intended to be written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively). SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
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... Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value. BANK 2 OFFSET 8 THROUGH Bh DATA REGISTER SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE READ/WRITE NOT EMPTY is a read only bit NOT READ Reserved EMPTY ...
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... The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A MASK bit being set will cause a hardware interrupt. Note : The Bit 7 mask must never be written high (1). SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME ...
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... RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. Receive Interrupt is cleared when RX FIFO is empty. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 32 ...
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... SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Figure 5.2 – Interrupt Structure Page 33 DATASHEET Datasheet Revision 1.0 (11-04-08) ...
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... With the proper memory structure, the search is limited to comparing only the multicast addresses that have the actual hash value in question. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
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... LOW CHIP BYTE 1 0 CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE READ/WRITE MDOE ...
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... BANK7 OFFSET 0 THROUGH 7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C110 when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE LOW BYTE SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications CHIP ID VALUE DEVICE 3 LAN91C90/LAN91C92 4 LAN91C94 5 LAN91C95 ...
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... Register. Write the packet number into the Packet Number Register. The corresponding status word is now readable from memory. If status word shows successful transmission, issue RELEASE SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications nCSOUT Driven low. Transparently latched on nADS rising edge ...
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... SERVICE INTERRUPT – Read Interrupt Status Register, exit the interrupt service routine. b) Option 1) Release the packet. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAC SIDE MAC SIDE The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state ...
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... Option 2) Check the transmit status in the EPH STATUS Register, write the packet number of the current packet to the Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAC SIDE Page 39 DATASHEET Datasheet Revision 1 ...
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... CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAC SIDE A packet is received with matching address. ...
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... Call TX INTR or TXEMPTY INTR Get Next TX Packet Available for Transmission? Yes Call ALLOCATE Call EPH INTR SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ISR Save Bank Select & Address Ptr Registers Mask SMC91C100FD Interrupts Read Interrupt Register No ...
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... SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes Destination No Multicast? Read Words from RAM for Address Filtering Address Yes No Filtering Pass? Yes No Status Word OK? Do Receive Lookahead ...
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... SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TX INTR Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg. Write Into Packet Number Register Write Address Pointer Register Read Status Word from RAM Yes TX Status ...
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... TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) Figure 5.6 - TXEMPTY INTR (Assumes auto release option selected) SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR ...
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... Write Source Address into Copy Remaining TX Data Set "Ready for Packet" Flag Return Buffers to Upper Layer Figure 5.7 - Drive Send and Allocate Routines SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ALLOCATE Issue "Allocate Memory" Command to MMU ...
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... TX EMPTY INT bit - Set whenever the TX FIFO is empty. AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and their memory is released automatically. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications The MMU allocates and de-allocates memory upon different events. ...
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... Transmit Status reading (interrupt driven). 1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also required from interrupt service routines. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 47 DATASHEET Datasheet Revision 1 ...
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... OPTIONS TX INT ALLOC INT 'NOT EMPTY' PACKET NUMBER Figure 5.8 – Interrupt Generation for Transmit, Receive, MMU SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications 'NOT EMPTY' PACKET NUMBER REGISTER 'EMPTY' TX DONE CPU ADDRESS M.S. BIT ONLY ...
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... CLK Low Input Level High Input Level Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications SYMBOL MIN TYP MAX V 0.8 ILI 2 ...
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... CAPACITANCE 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance CAPACITIVE LOAD ON OUTPUTS ARDY, D0-D15 240 pF All other outputs 45 pF SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications SYMBOL MIN TYP MAX V 0 -10 +10 ...
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... Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t8 A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE1 Hold after nADS Rising SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications A1-A15, AEN, nBE0-nBE1 valid D0-D15 valid ...
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... Figure 7.3 – Address Latching for All Modes PARAMETER t8 A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE1 Hold After nADS Rising t25 A4-A15, AEN to nLDEV Delay SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications t8 t9 A1-A15, AEN, nBE0-nBE1 t25 MIN TYP ...
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... Read – RD0-RD31 Hold after RA2-RA16 Change t52 Read – nROE enable to RD0-RD31 Valid t53 Read – nROE disable to RD0-RD31 Invalid t50 Read/Write – Cycle Time SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications t50 t50 t54 t35 t38 ...
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... IDT71016S15 4 IDT IDT71256SA12 3 IDT IDT71256SA15 3 SamSung K6E0808C1E-C10 3 SamSung K6E0808C1E-C12 3 SamSung K6E0808C1E-C15 3 SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications APPLICATION NOTE t38 R/W Output nROE Address Cycle Enable to Disable to Valid to Output Output in Data Valid Valid High Z ...
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... TXD0-TXD3, TXEN100 Delay from TX25 Rising t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications t27 t27 Figure 7.5 - MII Interface Page 55 ...
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... Note 4: Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.78-1.08 mm. Note 5: Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAX 1 ...