LAN9116-MD SMSC, LAN9116-MD Datasheet - Page 37
LAN9116-MD
Manufacturer Part Number
LAN9116-MD
Description
Ethernet ICs Efficient Sngl Chip 10/100 Ethrnt
Manufacturer
SMSC
Type
Single Chip MAC and PHYr
Datasheet
1.LAN9116-MT.pdf
(132 pages)
Specifications of LAN9116-MD
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9116
3.9.2.2
3.9.2.3
3.9.2.4
EEDIO (OUTPUT)
EEDIO (INPUT)
EECLK
EECS
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the
contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit
is set if the EEPROM does not respond within 30ms.
Table 3.8, "Required EECLK
each EEPROM operation.
MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.
If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be
un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates
a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC
address.
EEPROM Command and Data Registers
Refer to
"E2P_DATA – EEPROM Data Register," on page 93
Supported EEPROM operations are described in these sections.
EEPROM Timing
Refer to
OPERATION
ERASE
WRITE
EWDS
EWEN
READ
WRAL
ERAL
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 91
Section 6.9, "EEPROM Timing," on page 124
1
0
0
Figure 3.10 EEPROM WRAL Cycle
Table 3.8 Required EECLK Cycles
0
Cycles", shown below, shows the number of EECLK cycles required for
1
DATASHEET
37
REQUIRED EECLK CYCLES
D7
for detailed EEPROM timing specifications.
for a detailed description of these registers.
D0
10
10
10
10
18
18
18
t
CSL
Revision 1.5 (07-11-08)
and
Section 5.3.24,
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