CS8900A-CQ Cirrus Logic Inc, CS8900A-CQ Datasheet - Page 61

• Manufacturer Part Number: CS8900A-CQ
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQ

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
TxUnderrun
RxMiss
Rx128
RxDest
Reset value is:
Notes: With any event register, like BufEvent, all bits are cleared upon readout. The host is responsible for
4.4.14 Register 10: Receiver Miss Counter
(RxMISS, Read-only, Address: PacketPage base + 0130h)
The RxMISS counter (Bits 6 through F) records the number of receive frames that are lost (missed) due to the lack
of available buffer space. If the MissOvfloiE bit (Register B, BufCFG, Bit D) is set, there is an interrupt when RxMISS
increments from 1FFh to 200h. This interrupt provides the host with an early warning that the RxMISS counter should
be read before it reaches 3FFh and starts over (by interrupting at 200h, the host has an additional 512 counts before
RxMISS actually overflows). The RxMISS counter is cleared when read.
010000
MissCount
Register’s value is: 0000 0000 0001 0000
4.4.15 Register 12: Transmit Collision Counter
(TxCOL, Read-only, Address: PacketPage base + 0132h)
The TxCOL counter (Bits 6 through F) is incremented whenever the 10BASE-T Receive Pair (RXD+ / RXD-) or AUI
Collision Pair (CI+ / CI-) becomes active while a packet is being transmitted. If the TxColOvfiE bit (Register B, Buf-
CS8900A
Crystal LAN™ Ethernet Controller
7
F
7
F
MissCount
ColCount
processing all event bits.
0000 0000 0000 1100
mit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an interrupt.
ceive buffers. If RxMissiE (Register B, BufCFG, Bit A) is set, there is an interrupt.
allow the host the option of preprocessing frame data before the entire frame is received. If
Rx128iE (Register B, BufCFG, Bit B) is set, there is an interrupt.
as defined in the RxCTL register (Register 5). This bit is useful as an early indication of an in-
coming frame. It will be earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE (Register
B, BufCFG, Bit F) is set, there is an interrupt.
Miss Counter. When reading this register, these bits will be 010000, where the LSB corre-
sponds to Bit 0.
This bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans-
If set, one or more receive frames have been lost due to slow movement of data out of the re-
This bit is set after the first 128 bytes of an incoming frame have been received. This bit will
When set, this bit shows that a receive frame has passed the Destination Address Filter criteria
These bits provide an internal address used by the CS8900A to identify this as the Receiver
The upper ten bits contain the number of missed frames.
E
E
6
6
D
D
5
5
CIRRUS LOGIC PRODUCT DATASHEET
C
C
4
4
MissCount
ColCount
B
B
3
3
010000
010010
A
A
2
2
1
9
1
9
0
8
0
8
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