ispGDX160V-5B272 Lattice, ispGDX160V-5B272 Datasheet - Page 20
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
ispGDX160V-5B272
Manufacturer Part Number
ispGDX160V-5B272
Description
Analog & Digital Crosspoint ICs USE ispGDX2
Manufacturer
Lattice
Datasheet
1.ISPGDX160VA-5BN208.pdf
(36 pages)
Specifications of ispGDX160V-5B272
Maximum Dual Supply Voltage
3.6 V
Minimum Dual Supply Voltage
2.3 V, 3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
2.5 V, 3.3 V
Supply Type
Dual
Configuration
Programmable
Package / Case
BGA-272
Input Level
TTL
Output Level
TTL
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ispGDX160V timings are specified with a GRP load
(fanout) of four I/O cells. The figure below shows the ∆
GRP Delay with increased GRP loads. These deltas
External Timing Parameters (Continued)
ispGDX160V Maximum
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0 4 10
20
∆
I/O Cell Fanout
GRP Delay vs. I/O Cell Fanout
19
30
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
which do not use the GRP have no fanout delay adder.
Specifications ispGDX160V
40
50
60
70