CS8900A-IQ3R Cirrus Logic Inc, CS8900A-IQ3R Datasheet - Page 57

• Manufacturer Part Number: CS8900A-IQ3R
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3R

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
4.4.9 Register 7: Transmit Configuration
(TxCFG, Read/Write, Address: PacketPage base + 0106h)
Each bit in TxCFG is an interrupt enable. When set, the interrupt is enabled as described below. When clear, there
is no interrupt.
000111
Loss-of-CRSiE
SQErroriE
TxOKiE
Out-of-windowiE
JabberiE
AnycolliE
16colliE
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM
is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0000 0111
Notes: Bit 8 (TxOKiE) and Bit B (AnycolliE) are interrupts for normal transmit operation. Bits 6, 7, 9, A, and F
Notes:are interrupts for abnormal transmit operation.
4.4.10 Register 8: Transmitter Event
(TxEvent, Read-only, Address: PacketPage base + 0128h)
TxEvent gives the event status of the last packet transmitted.
CS8900A
Crystal LAN™ Ethernet Controller
SQE erroriE Loss-of-CRSiE
SQEerror
16colliE
16coll
7
F
7
F
Loss-of-CRS
Configuration Register.
end of the preamble, an interrupt is generated if this bit is set. Carrier Sense activity is reported
by the CRS bit (Register 14, LineST, Bit E).
the AUI, the CS8900A expects to see a collision within 64 bit times. If this does not happen,
there is an SQE error.)
occurs after the first 512 bit times). When this occurs, the CS8900A forces a bad CRC and ter-
minates the transmission.
curs at the end of the transmission
the CS8900A stops attempting to transmit that packet. When this bit is set, there is an interrupt
upon detecting the 16th collision.
These bits provide an internal address used by the CS8900A to identify this as the Transmit
If the CS8900A starts transmitting on the AUI and does not see the Carrier Sense signal at the
When set, an interrupt is generated if there is an SQE error. (At the end of a transmission on
When set, an interrupt is generated if a packet is completely transmitted.
When set, an interrupt is generated if a late collision occurs (a late collision is a collision which
When set, an interrupt is generated if a transmission is longer than approximately 26 ms.
When set, if one or more collisions occur during the transmission of a packet, an interrupt oc-
If the CS8900A encounters 16 normal collisions while attempting to transmit a particular packet,
E
E
6
6
Number-of-Tx-collisions
D
D
5
5
CIRRUS LOGIC PRODUCT DATASHEET
C
C
4
4
AnycolliE
B
B
3
3
001000
000111
JabberiE
Jabber
A
A
2
2
Out-of-window
Out-of-window
1
9
1
9
TxOKiE
TxOK
0
8
0
8
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