CS8900A-CQ3R Cirrus Logic Inc, CS8900A-CQ3R Datasheet - Page 60

• Manufacturer Part Number: CS8900A-CQ3R
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQ3R

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RxMissiE
Rx128iE
TxColOvfiE
MissOvfloiE
RxDestiE
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state after reset. If an
EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0000 1011
4.4.13 Register C: Buffer Event
(BufEvent, Read-only, Address: PacketPage base + 012Ch)
BufEvent gives the status of the transmit and receive buffers.
001100
SWint
RxDMAFrame
Rdy4Tx
RxDMA frame
60
RxDest
7
F
SWint
host still wants to transmit that particular frame, the host must go through the transmit request
process again.
receive data out of the receive buffer (called a receive miss). When this happens, the RxMiss
bit (Register C, BufEvent, Bit A) is set.
lows a host processor to examine the Destination Address, Source Address, Length, Sequence
Number, and other information before the entire frame is received. This interrupt should not be
used with DMA. Thus, if either AutoRxDMA (Register 3, RxCFG, Bit A) or RxDMAonly (Register
3, RxCFG, Bit 9) is set, the Rx128iE bit must be clear.
counter (Register 18) is incremented whenever the CS8900A sees that the RXD+/RXD- pins
(10BASE-T) or the CI+/CI- pins (AUI) go active while a packet is being transmitted.)
200h. (A receive miss is said to have occurred if packets are lost due to slow movement of re-
ceive data out of the receive buffers. When this happens, the RxMiss bit (Register C, BufEvent,
Bit A) is set, and the RxMISS counter (Register 10) is incremented.)
teria defined in the RxCTL register (Register 5). This bit provides an early indication of an in-
coming frame. It is earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE is set, the
BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from
RxDest to Rx128.
Register. When reading this register, these bits will be 001100, where the LSB corresponds to
Bit 0.
X bit (Register B, BufCFG, Bit 6).
B, BufCFG, Bit 7) is set, there is an interrupt.
ister B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 5.6 on page 99 for a description
of the transmit bid process.)
When set, there is an interrupt if one or more received frames is lost due to slow movement of
When set, there is an interrupt after the first 128 bytes of a frame have been received. This al-
If set, there is an interrupt when the TxCOL counter increments from 1FFh to 200h. (The TxCOL
If MissOvfloiE is set, there is an interrupt when the RxMISS counter increments from 1FFh to
When set, there is an interrupt when a receive frame passes the Destination Address filter cri-
These bits provide an internal address used by the CS8900A to identify this as the Buffer Event
If set, there has been a software initiated interrupt. This bit is used in conjunction with the SWint-
If set, one or more received frames have been transferred by slave DMA. If RxDMAiE (Register
If set, the CS8900A is ready to accept a frame from the host for transmission. If Rdy4TxiE (Reg-
E
6
D
5
CIRRUS LOGIC PRODUCT DATASHEET
C
4
Rx128
B
3
001100
Crystal LAN™ Ethernet Controller
RxMiss
A
2
TxUnder run
1
9
CS8900A
Rdy4Tx
DS271F5
0
8