COM20020I-HD SMSC, COM20020I-HD Datasheet - Page 24

• Manufacturer Part Number: COM20020I-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20020I-HD

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6
6.1
The COM20020I 3V contains an internal microsequencer which performs all of the control operations necessary to
carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, two instruction
registers, an instruction decoder, a no-op generator, jump logic, and reconfiguration logic.
The COM20020I 3V derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier. These clocks
provide the rate at which the instructions are executed within the COM20020I 3V. The 10 MHz clock is the rate at
which the program counter operates, while the 5 MHz clock is the rate at which the instructions are executed. The
microprogram is stored in the ROM and the instructions are fetched and then placed into the instruction registers.
One register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is
decoded by the internal instruction decoder, at which point the COM20020I 3V proceeds to execute the instruction.
When a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is
temporarily stopped until the loop is complete. When a jump instruction is encountered, the program counter is loaded
with the jump address from the ROM. The COM20020I 3V contains an internal reconfiguration timer which interrupts
the microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of the
Diagnostic Status Register is set.
Note*: (R/W) These bits can be Written or Read. For more information see Appendix C.
SMSC COM20020I 3.3V Rev.E
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
REGISTER
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
SUB ADR
URATION
CONFIG-
NODE ID
SETUP1
NEXT ID
SETUP2
STATUS
STATUS
TENTID
DIAG.
DATA
Microsequencer
MY-RECON
RBUS-TMG
P1 MODE
RD-DATA
NXT ID7
RESET
(R/W)*
RI/TRI
MSB
TID7
NID7
D7
A7
Functional Description
DUPID
AUTO-
(R/W)*
CCHE
FOUR
NAKS
NID6
TID6
X/RI
NXT
INC
ID6
A6
D6
N
X
Table 2 - Read Register Summary
TXEN
RCV-
NID5
X/TA
TID5
ACT
NXT
ID5
D5
A5
X
X
X
X
DATASHEET
TOKEN
CKUP
RCV-
NID4
POR
TID4
NXT
Page 24
ET1
ALL
ID4
A4
D4
X
X
READ
EXC-N
TEST
CKP3
NID3
TID3
NXT
ET2
ID3
AK
D3
EF
A3
X
X
SUB-AD
NO-SYN
BACK-P
RECON
TENTID
LANE
CKP2
NID2
TID2
NXT
A10
ID2
A2
D2
C
2
NEXT
CKP1
RCN-
SUB-
SUB-
NEW
NID1
TMA
TID1
NXT
TM1
AD1
AD1
ID1
A9
A1
D1
ID
SLOW-
RCM-T
SUB-A
SUB-A
NID0
TID0
LSB
ARB
NXT
TTA
TA/
ID0
M2
A8
A0
D0
D0
D0
X
Revision 09-11-06
ADDR
07-0
07-1
07-2
07-3
07-4
00
01
02
03
04
05
06