COM20020ILJPTR SMSC, COM20020ILJPTR Datasheet
COM20020ILJPTR
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COM20020ILJPTR Summary of contents
Page 1
... Software Programmable Node ID COM20020ILJP for 28 pin PLCC package COM20020I-DZD for 28 pin PLCC lead-free RoHS compliant package COM20020I-HD for 48 pin TQFP package COM20020I-HT for 48 pin TQFP lead-free RoHS compliant package SMSC COM20020I Rev D COM20020I Rev D 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“ ...
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... Selecting RAM Page Size ...................................................................................................................41 6.4.2 Transmit Sequence .............................................................................................................................42 6.4.3 Receive Sequence ..............................................................................................................................44 6.5 Command Chaining....................................................................................................................................45 6.5.1 Transmit Command Chaining .............................................................................................................45 6.5.2 Receive Command Chaining ..............................................................................................................46 6.6 Reset Details..............................................................................................................................................47 6.6.1 Internal Reset Logic ............................................................................................................................47 6.7 Initialization Sequence ...............................................................................................................................47 6.7.1 Bus Determination...............................................................................................................................47 SMSC COM20020I Rev D Page 3 DATASHEET Revision 12-05-06 ...
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... Table 6.5 - Command Register.....................................................................................................................................33 Table 6.6 - Address Pointer High Register ....................................................................................................................34 Table 6.7 - Address Pointer Low Register.....................................................................................................................34 Table 6.8 - Sub Address Register .................................................................................................................................34 Table 6.9 - Configuration Register ................................................................................................................................35 Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 4 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... For more detailed information on cabling options including RS485, transformer-coupled RS-485 and Fiber Optic interfaces, please refer to the following technical note which is available from Standard Microsystems Corporation: Technical Note 7-5 - Cabling Guidelines for the COM20020 ULANC. SMSC COM20020I Rev D Page 5 DATASHEET Revision 12-05-06 ...
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... Chapter 1 General Description SMSC's COM20020ID is a member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial, automotive, and embedded control environments ® using an ARCNET protocol engine. The small 28 pin package, flexible microcontroller and media interfaces, eight- page message support, and extended temperature range of the COM20020ID make it the only true network controller optimized for use in industrial, embedded, and automotive applications ...
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... VDD A0/nMUX A2/ALE 3 AD0 Ordering Information: COM20020 I LJP PACKAGE TYPE: "LJP" = Standard (Sn/Pb) plated PLCC TEMP RANGE: DEVICE TYPE: Figure 2.1 - Pin Configuration - COM20020I 28-Pin PLCC SMSC COM20020I Rev Package: 28-Pin PLCC "-DZD" = Pb-free plated PLCC (Blank) = Commercial = 0°C to +70°C " ...
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... D3 7 VDD VSS Figure 2.2 - Pin Configuration - COM20020I 48-Pin TQFP Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM COM20020I 48 PIN TQFP Page 8 DATASHEET Datasheet 36 nCS 35 VDD 34 nINTR 33 N/C 32 VDD 31 nRESET 30 VSS 29 nTXEN 28 RXIN 27 N/C 26 BUSTMG 25 nPULSE2 SMSC COM20020I Rev D ...
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... Select 19,18 nPulse 2, nPulse 1 20 Receive In SMSC COM20020I Rev D SYMBOL MICROCONTROLLER INTERFACE A0/nMUX, Input non-multiplexed mode, A0-A2 are address input bits. (A0 is the LSB multiplexed address/data A1,A2/ALE bus, nMUX tied Low left open, and ALE is tied to the Address Latch Enable signal connected to an internal pull-up resistor ...
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... An external crystal should be connected to these pins. Oscillation frequency range is from MHz XTAL2 external TTL clock is used instead, it must be connected to XTAL1 with a 390Ω pull-up resistor, and XTAL2 should be left floating Volt Power Supply pin Ground pin. SS Page 10 DATASHEET Datasheet DESCRIPTION SMSC COM20020I Rev D ...
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... DID refers to the destination identification. - SOH refers to the start of header character; preceeds all data packets. * Reconfig timer is programmable via setup2 register bits 1, 0. Note - All time values are valid for 5 Mbps. SMSC COM20020I Rev D Power On Send Reconfigure Burst Read Node ID Write ID to ...
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... Setup2 register, CKUP[1,0] as shown below. The selected clock is supplied to the ARCNET controller. Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM TIMEOUT SCALING FACTOR DATA RATE 5 Mbps 2.5 Mbps 1.25 Mbps 625 Kbps 312.5 Kbps 156.25 Kbps Page 12 DATASHEET Datasheet If the packet is received (MULTIPLY BY SMSC COM20020I Rev D ...
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... The NETWORK RECONFIGURATION time depends on the number of nodes in the network, the propagation delay between nodes, and the highest ID number on the network, but is typically within the range 30.5 mS. SMSC COM20020I Rev D CLOCK FREQUENCY (DATA RATE MHz (Up to 2.5Mbps) Default (Bypass) ...
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... Unlike asynchronous protocols, there is a constant amount of time separating each data byte Mbps network, each byte takes exactly 11 clock intervals of 200ns Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 14 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... COUNT character if a long packet is sent. N data bytes where COUNT = 256-N (or 512-N for a long packet) Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X ALERT SOH SID BURST SMSC COM20020I Rev D ALERT EOT DID BURST ALERT ENQ ...
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... A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM ALERT BURST ACK ALERT BURST NAK Page 16 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... RAM. During a write operation, the data is stored in the data register and then written into memory. Whenever the pointer is loaded for reads with a new value, data is immediately prefetched to prepare for the first read operation. SMSC COM20020I Rev D Page 17 DATASHEET ...
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... GND nINTR XTAL1 XTAL2 A0/nMU MHz XTAL +5V RXIN 100 nPULSE NOTE: COM20020 must be in backplane mode Page 18 DATASHEET Datasheet 75176B or Equiv. Differential Configuratio Media * may be with Figure +5V 2 Receive 6 HFD3212- 7 Transmitte HFE4211 Fiber (ST FIGURE B SMSC COM20020I Rev D ...
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... XTAL1 XTAL2 D0- nRES nIOS R/nW nIRQ1 6801 RXIN nTXEN nPULSE1 nPULSE2 GND Figure 5.2 – Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface SMSC COM20020I Rev D COM20020ID D0-D7 A0/nMUX RXIN A1 A2/BALE TXEN nCS nPULSE1 nRESET nPULSE2 nRD/nDS GND nWR/nDIR nINTR XTAL1 XTAL2 ...
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... The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function defined as: RBUSTMG=0, Disabled (Default); RBUSTMG=1, Enabled. Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID VALID Page 20 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... RXIN pulses to NRZ format. Figure 5.4 illustrates the events which occur in transmission or reception of data consisting Note: Please refer to TN7-5 – Cabling Guidelines for the COM20020 ULANC, available from SMSC, for recommended cabling distance, termination, and node count for ARCNET nodes. 5.2.2 ...
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... For applications requiring different treatment Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM +VCC +VCC RBIAS RBIAS COM20020ID 1 1 100ns 400ns Page 22 DATASHEET Datasheet RT +VCC RBIAS COM20020ID 0 SMSC COM20020I Rev D ...
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... To retain the normal active low polarity, nPULSE2 should be left open. determination is made at power on reset and is valid only for Backplane Mode operation. The nPULSE2 pin should remain grounded at all times if an active high polarity is desired. SMSC COM20020I Rev D Page 23 DATASHEET coupled ...
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... Table 5.1 - Typical Media NOMINAL IMPEDANCE 93Ω 75Ω 75Ω 150Ω 100Ω 105Ω Page 24 DATASHEET Datasheet ADDITIONAL REGISTERS nPULSE1 nPULSE2 TX/RX nTXEN LOGIC RXIN XTAL1 OSCILLATOR XTAL2 LOGIC ATTENUATION PER 1000 FT MHZ 5.5dB 7.0dB 5.5dB 7.0dB 17.9dB 16.0dB SMSC COM20020I Rev D ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485 and Fiber Optic interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020 ULANC, available from Standard Microsystems Corporation. SMSC COM20020I Rev D Page 25 DATASHEET Revision 12-05-06 ...
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... TTA NEW 01 X NEXTID 02 A10 SUB- SUB- 05 AD2 AD1 AD0 SUB- SUB- 06 AD1 AD0 07-0 TID2 TID1 TID0 NID2 NID1 NID0 07-1 CKP1 SLOW- 07-2 ARB NXT NXT NXT 07-3 ID1 ID0 ID2 07-4 NO- RCN- RCM- TM1 TM2 SMSC COM20020I Rev D ...
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... A RECON interrupt is cleared when the "Clear Flags" command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A SMSC COM20020I Rev D Table 6.2 - Write Register Summary WRITE ...
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... Each time the microsequencer updates the Next ID Register, a New Next ID interrupt is generated. This bit is cleared by reading the Next ID Register. Default value is 0000 0000 upon hardware or software reset. Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 28 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... The COM20020ID Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20020ID, the COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration Register ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM If this bit is reset, the line has to be idle for the RAM TIME-OUT MAX NODE RCNTM0 PERIOD 0 420 255 nodes 1 105 nodes 0 52 nodes 1 26.25 mS nodes Note 6.3 Page 30 DATASHEET Datasheet COUNT SMSC COM20020I Rev D ...
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... Acknowledged 0 Transmitter TA Available SMSC COM20020I Rev D Table 6.3 - Status Register DESCRIPTION This bit, if high, indicates that the receiver is not enabled because either an "Enable Receive to Page fnn" command was never issued packet has been deposited into the RAM buffer page fnn as specified by the last " ...
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... Reading the Diagnostic Status Register does not clear this bit. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. The bit is cleared by reading the Next ID Register. These bits are undefined. Page 32 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... Receive Interrupt 0001 1000 Start Internal Operation SMSC COM20020I Rev D Table 6.5 - Command Register DESCRIPTION This command is used only in the Command Chaining operation. Please refer to the Command Chaining section for definition of this command. This command will cancel any pending transmit command (transmission that has not yet started) and will set the TA (Transmitter Available) status bit to logic " ...
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... SUBAD1 and SUBAD0 are exactly the same as exist in the Configuration Register. SUBAD2 is cleared automatically by writing the Configuration Register. Page 34 DATASHEET Datasheet DESCRIPTION DESCRIPTION DESCRIPTION SUBAD0 Register 0 Tentative ID \ (Same 1 Node Setup 1 / Config 1 Next ID / Register) 0 Setup 2 1 Reserved 0 Reserved 1 Reserved SMSC COM20020I Rev D ...
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... This bit, if high, enables the Command Chaining operation of the device. Please refer to the Command Chaining section for further details. A low level on this bit ensures software compatibility with previous SMSC ARCNET devices. When low, this bit disables transmissions by keeping nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive. ...
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... This bit, when set, will divide the arbitration clock by 2. Memory cycle times will increase when slow arbitration is selected. NOTE: For clock multiplier output clock speeds greater than 40 MHz, SLOWARB must be set. Defaults to low. Page 36 DATASHEET Datasheet SPEED 2.5Mbs 1.25Mbs 625Kbs 312.5Kbs 156.25Kbs SMSC COM20020I Rev D ...
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... Enhanced Functions Synchronous NOSYNC SMSC COM20020I Rev D Table 6.11 - Setup 2 Register DESCRIPTION This bit is used to Disable/Enable the High Speed CPU Read function for High Speed CPU bus support. RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. It does not influence write operation. High speed CPU Read operation is only for non- multiplexed bus ...
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... Mbps. RCNTM1 RCNTM0 Time Out Period 0 0 420 105 52 26.25 mS* Note*: The node ID value 255 must exist in the network for 26.25 mS timeout to be valid. Page 38 DATASHEET Datasheet Max Node Count Up to 255 nodes nodes nodes nodes SMSC COM20020I Rev D ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet D0-D7 I/O Address 02H SMSC COM20020I Rev D Data Register I/O Address 04H Memory Data Bus 8 Address Pointer Register I/O Address 03H High Low Memory Address Bus 11-Bit Counter 11 Figure 6.1 - Sequential Access Operation ...
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... Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer) The pointer may now be read to determine how many transfers were completed. Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 40 DATASHEET Datasheet The SMSC COM20020I Rev D ...
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... Command Chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1K free). The general rule which may be applied to determine where in RAM a page begins is as follows: Address = (nn x 512 256). SMSC COM20020I Rev D Page 41 DATASHEET The ...
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... COUNT = 256 NOT USED DATA BYTE 1 DATA BYTE 2 COUNT DATA BYTE N-1 DATA BYTE N NOT USED 511 Page 42 DATASHEET Datasheet LONG PACKET FORMAT SID DID 0 COUNT = 512-N NOT USED DATA BYTE 1 DATA BYTE 2 DATA BYTE N-1 DATA BYTE N SMSC COM20020I Rev D ...
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... These situations can be determined by either using the improved diagnostic features of the COM20020ID or using another software timeout which is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum length message. SMSC COM20020I Rev D Page 43 DATASHEET ...
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... MSB TRI RI TRI Figure 6.3 – Command Chaining Status Register Queue Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM TA POR TEST RECON Page 44 DATASHEET Datasheet LSB TMA TTA TMA TTA SMSC COM20020I Rev D ...
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... Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM20020ID to be compatible with previous SMSC ARCNET device drivers, the device defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode must be enabled via a logic " ...
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... TRI bit of the Status Register. In Command Chaining mode, the "Disable Receiver" command will cancel the oldest reception, unless the reception has already begun. If both receptions should be canceled, two "Disable Receiver" commands should be issued. Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 46 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... Node ID is found. At this point, the TX Enable bit may be set to allow the node to join the network. Once the node joins the network, a reconfiguration occurs, as usual, thus setting the MYRECON bit of the Diagnostic Status Register. SMSC COM20020I Rev D This pulse width is used by the internal digital filter, which XTL. ...
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... Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Reading the Diagnostic Status Register resets the MYRECON bit. Page 48 DATASHEET Datasheet The SMSC COM20020I Rev D ...
Page 49
... The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock for other devices. The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390Ω pull-up resistor is required on XTAL1, while XTAL2 should be left unconnected. SMSC COM20020I Rev D Page 49 DATASHEET Revision 12-05-06 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM COM20020I SYMBOL MIN TYP V IL1 V 2.0 IH1 V IL2 V 4.0 IH2 V 1.8 ILH V 1.2 IHL Page 50 DATASHEET Datasheet + +150 DD MAX UNIT COMMENT 0.8 V TTL Levels V TTL Levels 1.0 V TTL Clock Input V V Schmitt Trigger, All Values SMSC COM20020I Rev +0.3V = ...
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... Low Output Voltage 4 (nPULSE1 in Open-Drain Mode) Dynamic V Supply DD Current Input Pull-up Current (nPULSE1 in Open-Drain Mode, A1, AD0-AD2, D3-D7) Input Leakage Current (All inputs except A1, AD0-AD2, D3-D7, XTAL1, XTAL2 SMSC COM20020I Rev D SYMBOL MIN TYP V OL1 V 2.4 OH1 V 0 OH1C DD V OL2 V 2 ...
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... Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM = 1MHz 0V MIN TYP MAX C 5 OUT1 400 OUT2 Outputs: t 2.0V 0.8V 2.0V 0.8V t Page 52 DATASHEET Datasheet UNIT COMMENT pF pF Maximum Capacitive Load which can be supported by each output. pF SMSC COM20020I Rev D ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.1 – Multiplexed Bus, 68XX-Like Control Signals; Read Cycle SMSC COM20020I Rev D VALID VALID DATA t1 t2, t4 ...
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... VALID DATA VALID t2 t10 t6 t5 t11 t13 Note 3 MUST BE: RBUSTMG bit = 0 Parameter if SLOW ARB = 0 opr from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 54 DATASHEET Datasheet t7 t8 t12 Note 2 min max units ARB SMSC COM20020I Rev D ...
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... Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle SMSC COM20020I Rev D VALID DATA VALID t2 t12 ...
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... Note 3 Parameter min Next )** 4T * ARB from the trailing edge of nWR to the leading edge of the ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 56 DATASHEET Datasheet t7 Note 2 t8** t8 t12 max units SMSC COM20020I Rev D ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle SMSC COM20020I Rev D VALID t1 t3 Note 3 t10 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t10 t8 t6 VALID DATA CASE 2: RBUSTMG bit = 1 Parameter min 4T ARB if SLOW ARB = 0 from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 58 DATASHEET Datasheet Note 2 t7 max units *+ 60 100 SMSC COM20020I Rev D ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle SMSC COM20020I Rev D VALID ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t10 t8 VALID DATA CASE 2: RBUSTMG bit = 1 Parameter 4T if SLOW ARB = 0 from the trailing edge of nDS to ARB Page 60 DATASHEET Datasheet t11 Note 2 t9 min max units - *+30 nS ARB 100 nS 30 SMSC COM20020I Rev D ...
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... Register requires a minimum of 5T leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle SMSC COM20020I Rev D VALID t10 t6 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t10 t8 VALID DATA min Next Time )** 4T ARB 10 30*** SLOW ARB = 0 from the trailing edge of nDS to the leading edge ARB from the trailing edge of nDS to ARB Page 62 DATASHEET Datasheet t11 Note 2 t6 max units SMSC COM20020I Rev D ...
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... Beginning of Last Bit Time to nTXEN High t6 RXIN Active Pulse Width t7 RXIN Period t8 RXIN Inactive Pulse Width Note: Use Only 2.5 Mbps Figure 8.11 - Normal Mode Transmit or Receive Timing (These signals are to and from the hybrid) SMSC COM20020I Rev min -10 850 250 ...
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... Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM t10 t12 t11 Parameter Page 64 DATASHEET Datasheet t13 t8 LAST BIT (400 nS BIT TIME) min typ max units - 200* nS 400 100* nS 100* nS 200 -25 650 750 nS 450 550 nS 10 200* nS 400 SMSC COM20020I Rev D ...
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... Pulse Width*** t2 nINTR High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of Data Rate (i.e. at 2.5 Mbps Note***: When the power is turned on measured from stable XTAL oscillation after V DD SMSC COM20020I Rev 1.0V min -200 + - t2 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM PIN 28L .160-.180 A .090-.120 .013-.021 .026-.032 B 1 .020-.045 C D .485-.495 .450-.456 .390-.430 D 3 .300 .050 BSC F .042-.056 G .042-.048 J .000-.020 R .025-.045 Page 66 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... H 0. 0.50 Basic o θ 0.17 R1 0.08 R2 0.08 ccc ~ ccc ~ Note 1: Controlling Unit: millimeter SMSC COM20020I Rev D Figure 9 Pin TQFP Package Outline MAX ~ 1.6 0.10 0.15 1.40 1.45 9.00 9.20 1 4.50 4. Span Measure from Centerline 2 7.00 7.10 9.00 9.10 1 4.50 4.60 ...
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... The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the Set-Up register. The CKP3-1 bits are changed by writing the Set-Up register from outside the CPU. It's not Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 68 DATASHEET Datasheet SMSC COM20020I Rev D ...
Page 69
... This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft reset. The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in the Configuration register. This solution is Enabled/Disabled by the EF bit. SMSC COM20020I Rev D Page 69 DATASHEET ...
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... Setting Pulse nINTR pin EF=1 TA/RI bit Setting Pulse nINTR pin Figure 0.1 - Effect of the EF Bit on the TA/RI Bit Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Tx/Rx completed prohibition period Tx/Rx completed Page 70 DATASHEET Datasheet SMSC COM20020I Rev D ...
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... ISA Bus ISA Bus AEN nG SA15-SA4 P 12 SD7-SD0 A 8 nIOR nIOW SA2-SA0 3 IRQm nIOCS16 DRQn nDACK TC nREFRESH RESETDRV SMSC COM20020I Rev D LS688x2 12 bit Comparators Q I/O Address Seeting (DIP Switches) P=Q 12 LS245 A 16 bit Bus Transceivers DIR 3 Schmitt-Trigger Buffer Page 71 DATASHEET COM20020 ...
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... If the value read from Register-5 is 0x00 then the part is a COM20020 Rev the value read from Register-5 is 0x80 then the part is a COM20020 Rev D Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 72 DATASHEET Datasheet SMSC COM20020I Rev D ...