SI7108DN-T1-E3 Vishay, SI7108DN-T1-E3 Datasheet - Page 7

• Manufacturer Part Number: SI7108DN-T1-E3
• Description: MOSFET N-CH 20V 14A 1212-8
• Manufacturer: Vishay
• Series: TrenchFET®r
• Type: Power MOSFETr

Specifications of SI7108DN-T1-E3

• Transistor Polarity: N-Channel
• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 4.9 mOhm @ 22A, 10V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 14A
• Vgs(th) (max) @ Id: 2V @ 250µA
• Gate Charge (qg) @ Vgs: 30nC @ 4.5V
• Power - Max: 1.5W
• Mounting Type: Surface Mount
• Package / Case: PowerPAK® 1212-8
• Minimum Operating Temperature: - 55 C
• Configuration: Single Quad Drain Triple Source
• Resistance Drain-source Rds (on): 0.0049 Ohm @ 10 V
• Forward Transconductance Gfs (max / Min): 88 S
• Drain-source Breakdown Voltage: 20 V
• Gate-source Breakdown Voltage: +/- 16 V
• Continuous Drain Current: 14 A
• Power Dissipation: 1500 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Continuous Drain Current Id: 22A
• Drain Source Voltage Vds: 20V
• On Resistance Rds(on): 4.9mohm
• Rds(on) Test Voltage Vgs: 10V
• Threshold Voltage Vgs Typ: 2V
• Number Of Elements: 1
• Polarity: N
• Channel Mode: Enhancement
• Drain-source On-res: 0.0049Ohm
• Drain-source On-volt: 20V
• Gate-source Voltage (max): ±16V
• Operating Temp Range: -55C to 150C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: PowerPAK 1212
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SI7108DN-T1-E3TR

Johnson Zhao
MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi-
ous that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a deriva-
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
Document Number 71681
03-Mar-06
PowerPAK
Figure 1. PowerPAK 1212 Devices
®
1212 Mounting and Thermal Considerations
The PowerPAK 1212-8 has a footprint area compara-
ble to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger pack-
ages are typically required solely for thermal consider-
ation, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 single in the index of this
document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in
ment in thermal performance.
2
of will yield little improve-
Vishay Siliconix
www.vishay.com
AN822
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