CS61577-IL1 Cirrus Logic Inc, CS61577-IL1 Datasheet - Page 17

• Manufacturer Part Number: CS61577-IL1
• Description: Network Controller & Processor ICs IC T1/E1 Low PWR Line Interface Unit
• Manufacturer: Cirrus Logic Inc

Specifications of CS61577-IL1

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Writing a "1" to either "Clear LOS" or "Clear
DPM" over the serial interface has three effects:
Writing a "0" to either "Clear LOS" or "Clear
DPM" enables the corresponding interrupt for
LOS or DPM.
Input bits 5/6/7=111 and 5/6/7=101 are the same
request, and cause the line interface to enter into
the factory test mode. In other words, when
RLOOP=1 (Bit 5) and TAOS=1 (Bit 7), LOOP
(Bit 6) is a don’t care. For normal operation,
RLOOP and TAOS should not be simultaneously
selected via the serial interface.
Output data from the serial interface is presented
as shown in Tables 11 and 12. Bits 2, 3 and 4 can
be read to verify line length selection. Bits 5, 6
and 7 must be decoded. Codes 101, 110 and 111
(Bits 5, 6 and 7) indicate intermittent losses of
signal and/or driver problems.
SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in appli-
cations where the host processor has a
bi-directional I/O port.
LSB: first bit in
1) The current interrupt on the serial interface
2) Output data bits 5, 6 and 7 will be reset as
3) Future interrupts for the corresponding LOS
will be cleared. (Note that simply reading
the register bits will not clear the inter-
rupt).
appropriate.
or DPM will be prevented from occurring.
Table 11. Output Data Bits 0 - 4
1
2
3
4
0
LEN0
LEN1
LEN2
DPM
LOS
Loss of Signal
Driver Performance Monitor
Bit 0 - Line Length Select
Bit 1 - Line Length Select
Bit 2 - Line Lenght Select
Power On Reset / Reset
Upon power-up, the IC is held in a static state
until the supply crosses a threshold of approxi-
mately 3 Volts. When this threshold is crossed,
the device will delay for about 10 ms to allow the
power supply to reach operating voltage. After
this delay, calibration of the delay lines used in
the transmit and receive sections commences. The
delay lines can be calibrated only if a reference
clock is present. The reference clock for the re-
ceiver is provided by the crystal oscillator, or
ACLKI if the oscillator is disabled. The reference
clock for the transmitter is provided by TCLK.
The initial calibration should take less than
20 ms.
In operation, the delay lines are continuously cali-
brated, making the performance of the device
independent of power supply or temperature vari-
ations. The continuous calibration function
forgoes any requirement to reset the line interface
when in operation. However, a reset function is
available which will clear all registers.
In the Hardware and Extended Hardware Modes,
a reset request is made by simultaneously setting
both the RLOOP and LLOOP pins high for at
least 200 ns. Reset will initiate on the falling edge
of the reset request (falling edge of RLOOP and
LLOOP). In the Host Mode, a reset is initiated by
simultaneously writing RLOOP and LLOOP to
5 6 7
0 0 0 Reset has occurred or no program input.
0 0 1 TAOS in effect.
0 1 0 LLOOP in effect.
0 1 1 TAOS/LLOOP in effect.
1 0 0 RLOOP in effect
1 0 1 DPM changed state since last "clear DPM"
1 1 0 LOS changed state since last "clear LOS"
1 1 1 LOS and DPM have changed state since
Bits
Table 12. Coding for Serial Output bits 5,6,7
occured.
occured.
last "clear LOS" and "clear DPM".
Status