COM20019I-DZD-TR SMSC, COM20019I-DZD-TR Datasheet - Page 30

• Manufacturer Part Number: COM20019I-DZD-TR
• Description: Network Controller & Processor ICs Arcnet Controller HP AutoMDIX
• Manufacturer: SMSC

Specifications of COM20019I-DZD-TR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev. 09-25-07
0000 c101
000r p110
0000 1000
7
6
5-3
2-0
7-0
BIT
BIT
DATA
Read Data
Auto Increment
(Reserved)
Address 10-8
Address 7-0
BIT NAME
BIT NAME
Define
Configuration
Clear Flags
Clear
Receive
Interrupt
COMMAND
RDDATA
AUTOINC
A10-A8
A7-A0
Table 6.6 - Address Pointer High Register
Table 6.7 - Address Pointer Low Register
SYMBOL
SYMBOL
DATASHEET
This command defines the maximum length of packets that may
be handled by the device. If "c" is a logic "1", the device
handles both long and short packets. If "c" is a logic "0", the
device handles only short packets.
This command resets certain status bits of the COM20019I. A
logic "1" on "p" resets the POR status bit and the EXCNAK
Diagnostic status bit. A logic "1" on "r" resets the RECON
status bit.
This command is used only in the Command Chaining
operation. Please refer to the Command Chaining section for
definition of this command.
This bit tells the COM20019I whether the following access
will be a read or write. A logic "1" prepares the device for
a read, a logic "0" prepares it for a write.
This bit controls whether the address pointer will
increment automatically. A logic "1" on this bit allows
automatic increment of the pointer after each access,
while a logic "0" disables this function. Please refer to the
Sequential Access Memory section for further detail.
These bits are undefined.
These bits hold the upper three address bits which
provide addresses to RAM.
These bits hold the lower 8 address bits which provide the
addresses to RAM.
Page 30
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
DESCRIPTION
DESCRIPTION
DESCRIPTION
SMSC COM20019I