LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 123

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
8.5.2.1
8.5.3
S
S
A
6
S
A
5
Control Byte
S
A
4
S
A
3
S
S
A
2
S
A
6
S
A
1
S
A
5
Figure 8.4
Control Byte
I
During reset, the I
is complete, the
read, the interface can be considered functional. At this point, the READY bit in the
Configuration Register (HW_CFG)
complete. Refer to
I
Following the device addressing, as detailed in
LAN9313/LAN9313i when the master continues to send data bytes. Each byte is acknowledged by the
LAN9313/LAN9313i. Following the fourth byte of the sequence, the master may either send another
start condition or halt the sequence with a stop condition. The internal register address is unchanged
following a single write.
Multiple writes are performed when the master sends additional bytes following the fourth
acknowledge. The internal address is automatically incremented and the next register is written. once
the internal address reaches it maximum value, it rolls over to 0. The multiple write is concluded when
the master sends another start condition or stop condition. The internal register address is incremented
for each write including the final. This is not relevant for subsequent writes, since a new register
address would be included on a new write cycle. However, this does affect the internal register address
if it were to be used for reads without first resetting the register address.
For both single and multiple writes, if the master sends an unexpected start or stop condition, the
LAN9313/LAN9313i will stop immediately and will respond to the next sequence as needed.
The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written
(master sends a start, or a stop condition occurs unexpectedly), the write is considered invalid and the
register is not affected. Multiple registers may be written in a multiple write cycle, each one being
written after 32-bits. I
S
A
0
2
2
S
A
4
C Slave Read Polling for Reset Complete
C Slave Write Sequence
0
S
A
3
A
C
K
S
A
2
A
9
S
A
1
A
8
Address Byte
S
A
0
A
7
illustrates a typical single and multiple register read.
0
A
6
C
A
K
A
5
A
9
A
4
Byte Order Test Register (BYTE_TEST)
Address Byte
A
8
A
3
2
A
7
C slave interface will not return valid data. To determine when the reset condition
Section 4.2, "Resets," on page 41
A
2
A
6
2
A
C
K
C writes must not be performed to unused register addresses.
A
5
S
A
4
S
A
6
A
3
S
A
5
Control Byte
A
2
Figure 8.4 I
S
A
4
A
C
K
S
A
3
S
S
A
2
S
A
6
DATASHEET
S
A
1
S
A
5
Multiple Register Reads
Control Byte
Single Register Read
S
A
0
can be polled to determine when the device initialization is
R/~W
S
A
4
1
S
A
3
A
C
K
2
123
S
A
2
C Slave Reads
D
3
1
Data 1 Byte
S
A
1
D
3
0
S
A
0
.. .
R/~W
1
A
C
K
D
2
5
D
3
1
D
2
4
D
3
0
for additional information.
A
C
K
Data Byte
Section
D
2
9
.. .
...Data m Byte
should be polled. Once the correct pattern is
D
2
8
S
2
7
D
4
D
2
6
D
3
D
2
5
8.5.1, a register is written to the
D
2
D
2
4
D
1
A
C
K
D
0
D
2
3
Data Byte...
A
C
K
D
2
2
D
3
1
Data m+1 Byte... ...Data n Byte
D
2
1
D
3
0
D
2
0
D
2
9
.. .
D
2
8
...Data Byte
D
2
7
D
5
Revision 1.7 (06-29-10)
D
2
6
D
4
.. .
D
3
D
2
D
1
D
4
D
D
0
3
Hardware
A
C
K
D
2
P
D
1
D
0
A
C
K
P