LAN8700IC-AEZG-TR SMSC, LAN8700IC-AEZG-TR Datasheet - Page 45

• Manufacturer Part Number: LAN8700IC-AEZG-TR
• Description: Ethernet ICs Hi Perform Ethernet PHY
• Manufacturer: SMSC
• Type: MII/RMII Ethernet Transceiverr

Specifications of LAN8700IC-AEZG-TR

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 802.3ab
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Supply Current (max): 39 mA, 81.6 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: QFN-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Datasheet
SMSC LAN8700/LAN8700i
ADDRESS
ADDRESS
ADDRESS
18.13:8
26.15:0
18.7:5
18.4:0
17.8:7
17.5:4
18.15
18.14
17.6
17.3
17.2
17.1
17.0
Good Link Status
Sym_Err_Cnt
ENERGYON
PHYADBP
Reserved
MIIMODE
Reserved
Reserved
Reserved
Reserved
PHYAD
ALTINT
NAME
MODE
NAME
NAME
Force
Table 5.38 Register 17 - Mode Control/Status (continued)
Table 5.40 Register 26 - Symbol Error Counter
Write as 0, ignore on read.
MII Mode: set the mode of the MII:
0 – MII interface.
1 – RMII interface
Write as 0, ignore on read.
PHY Mode of operation. Refer to
"Mode Bus – MODE[2:0]," on page 54
details.
PHY Address.
The PHY Address is used for the SMI address and for
the initialization of the Cipher (Scrambler) key. Refer
to
PHYAD[4:0]," on page 53
Write as 0, ignore on read.
Alternate Interrupt Mode.
0 = Primary interrupt system enabled (Default).
1 = Alternate interrupt system enabled.
See
Write as 0, ignore on read.
1 = PHY disregards PHY address in SMI access
0 = normal operation;
1 = force 100TX- link active;
Note:
ENERGYON – indicates whether energy is detected
on the line (see
Power-Down," on page
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
Write as 0. Ignore on read.
100Base-TX receiver-based error register that
increments when an invalid code symbol is received
including IDLE symbols. The counter is incremented
only once per packet, even when the received packet
contains more than one symbol error. The 16-bit
register counts up to 65,536 (2
if incremented beyond that value. This register is
cleared on reset, but is not cleared by reading the
register. It does not increment in 10Base-T mode.
Table 5.39 Register 18 - Special Modes
Section 5.4.9.1, "Physical Address Bus -
write.
Section 5.3, "Interrupt Management," on page
This bit should be set only during lab testing
DATASHEET
Section 5.4.5.2, "Energy Detect
®
DESCRIPTION
DESCRIPTION
DESCRIPTION
45
Technology in a Small Footprint
50); it goes to “0” if no valid
for more details.
16
) and rolls over to 0
Section 5.4.9.2,
for more
48.
MODE
MODE
MODE
NASR
NASR
NASR
NASR
RW,
RW,
RW,
RW,
Revision 2.2 (12-04-09)
RW
RW
RW
RW
RW
RW
RO
RW
RO
DEFAULT
DEFAULT
DEFAULT
EVB8700
EVB8700
000000
PHYAD
default
default
11111
XXX
111
00
00
0
0
X
0
0
0
X
0