LAN9215-MZP SMSC, LAN9215-MZP Datasheet - Page 17

Ethernet ICs 16-BIT NON-PCI 10/100 ETHERNET CTRL

LAN9215-MZP

Manufacturer Part Number
LAN9215-MZP
Description
Ethernet ICs 16-BIT NON-PCI 10/100 ETHERNET CTRL
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet

Specifications of LAN9215-MZP

Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
69 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9215-MZP
Manufacturer:
SMSC
Quantity:
17 600
Part Number:
LAN9215-MZP
Manufacturer:
SMSC
Quantity:
20 000
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9215
2.1
SPEED_SEL
Host Address
PHY External Bias
Read Strobe
Write Strobe
FIFO Select
Chip Select
Host Data
Interrupt
Request
NAME
Resistor
0
1
NAME
TPO+
TPO-
TPI+
TPI-
Pin List
FIFO_SEL
SYMBOL
D[15:0]
A[7:1]
100Mbps
nWR
nRD
nCS
10Mbps
IRQ
SPEED
SYMBOL
EXRES1
TPO+
TPO-
TPI+
TPI-
BUFFER
O8/OD8
Table 2.1 Host Bus Interface Signals
Table 2.2 Default Ethernet Settings
TYPE
I/O8
Table 2.3 LAN Interface Signals
IS
IS
IS
IS
IS
BUFFER
TYPE
AO
AO
AI
AI
AI
DEFAULT ETHERNET SETTINGS
DATASHEET
PINS
16
#
7
1
1
1
1
1
Half-Duplex
Half-Duplex
DUPLEX
PINS
NUM
17
1
1
1
1
1
Bi-directional data port.
7-bit Address Port. Used to select Internal CSR’s and
TX and RX FIFOs.
Active low strobe to indicate a read cycle.
Active low strobe to indicate a write cycle. This signal,
qualified with nCS, is also used to wakeup the
LAN9215 when it is in a reduced power state.
Active low signal used to qualify read and write
operations. This signal qualified with nWR is also used
to wakeup the LAN9215 when it is in a reduced power
state.
Programmable Interrupt request. Programmable
polarity, source and buffer types.
When driven high all accesses to the LAN9215 are to
the RX or TX Data FIFOs. In this mode, the A[7:3]
upper address inputs are ignored.
Transmit Positive Output (normal)
Receive Positive Input (reversed)
Transmit Negative Output (normal)
Receive Negative Input (reversed)
Receive Positive Input (normal)
Transmit Positive Input (reversed)
Receive Negative Input (normal)
Transmit Negative Output (reversed)
Must be connected to ground through a 12.4K
ohm 1% resistor.
DESCRIPTION
DESCRIPTION
AUTO NEG.
Disabled
Enabled
Revision 2.7 (03-15-10)

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