CS8900A-CQ3ZR Cirrus Logic Inc, CS8900A-CQ3ZR Datasheet - Page 91

• Manufacturer Part Number: CS8900A-CQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS271F5
5.3.3 DMA Receive Buffer Size
In receive DMA mode, the CS8900A stores re-
ceived frames (along with their status and
length) in a circular buffer located in host mem-
ory space. The size of the circular buffer is de-
termined by the RxDMAsize bit (Register 17,
BusCTL, Bit D). When RxDMAsize is clear, the
buffer size is 16 Kbytes. When RxDMAsize is
set, the buffer is 64 Kbytes. It is the host's task
to locate and keep track of the DMA receive
buffer's base address. The DMA Start-of-
Frame register is the only circuit affected by
this bit.
APPLICATION NOTE: As a result of the PC
architecture, DMA cannot occur across a 128K
boundary in memory. Thus, the DMA buffer re-
served for the CS8900A must not cross a
128K boundary in host memory if DMA opera-
tion is desired. Requesting a 64K, rather than
a 16K buffer, increases the probability of
crossing a 128K boundary. After the driver re-
quests a DMA buffer, the driver must check for
a boundary crossing. If the boundary is
crossed, then the driver must disable DMA
functionality.
5.3.4 Receive-DMA-Only Operation
If space is available, an incoming frame is tem-
porarily stored in on-chip RAM. When the en-
tire frame has been received, pre-processed,
and accepted, the CS8900A signals the DMA
CS8900A
Crystal LAN™ Ethernet Controller
PacketPage
Address
002Ah
0028h
Table 27. Receive DMA Registers
DMA Frame Count: The lower 12 bits
define the number of valid frames
transferred via DMA since the last
read-out of this register. The upper 4
bits are reserved and not applicable.
DMA Byte Count: Defines the num-
ber of bytes that have been transferred
via DMA since the last read-out of this
register.
Register Description
CIRRUS LOGIC PRODUCT DATASHEET
controller that a frame is to be transferred to
host memory by driving the selected DMA Re-
quest pin high. The DMA controller acknowl-
edges the request by driving the DMA
Acknowledge pin low. The CS8900A then
transfers the contents of the RxStatus register
(PacketPage base + 0400h) and the RxLength
register (PacketPage base + 0402h) to host
memory, followed by the frame data. If the
DMABurst bit (Register 17, BusCTL, Bit B) is
clear, the DMA Request pin remains high until
the entire frame is transferred. If the DMABurst
bit is set, the DMA Request pin (DMARQ) re-
mains high for approximately 28 μs then goes
low for approximately 1.3 μs to give the CPU
and other peripherals access to the bus.
When the transfer is complete, the CS8900A
does the following:
•
•
•
•
•
In addition, if the RxDMAiE bit (Register B,
BufCFG, Bit 7) is set, a corresponding inter-
rupt occurs.
When the host processes DMAed frames, it
must read the DMA Frame Count register.
Whenever a receive frame is missed (lost) due
to insufficient receive buffer space, the Rx-
MISS counter (Register 10) is incremented. A
missed receive frame causes the counter to in-
crement in either DMA or non-DMA modes.
updates the DMA Start-of-Frame register
(PacketPage base + 0026h);
updates the DMA Frame Count register
(PacketPage base + 0028h);
updates DMA Byte Count register (Packet-
Page base + 002Ah);
sets the RxDMAFrame bit (Register C,
BufEvent, Bit 7); and,
deallocates the buffer space used by the
transferred frame.
91