78Q8430-128CGTR/F Maxim Integrated Products, 78Q8430-128CGTR/F Datasheet - Page 12
78Q8430-128CGTR/F
Manufacturer Part Number
78Q8430-128CGTR/F
Description
Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
Manufacturer
Maxim Integrated Products
Datasheet
1.78Q8430-ARM9-EVM.pdf
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78Q8430 Data Sheet
3 Pin Description
3.1
Table 1 lists the different pin types found on the 78Q8430 device. The Type field of the pin description
tables refers to one of these types.
3.2
The pin descriptions in the following tables are grouped by interface. A pin number, type specification per
Table 2 and a functional description is provided for each pin on the 78Q8430 device.
3.2.1
12
Signal
XTLP
XTLN
BUSCLK
Pin Legend
Pin Descriptions
Clock Pins
Pin Number
87
88
15
Type
Type
OD
OZ
IU
IS
ID
O
G
A
S
B
I
A
I
Table 2: Clock Pin Descriptions
Description
Crystal Positive/Negative
To use the internal oscillator, connect a 25 MHz crystal across
XTLP and XTLN. To use of an external clock, XTLN is grounded
and XTLP is driven with a 25 MHz clock.
Provides timing reference for all media dependant interface
operations. An internal PLL is used to multiply this clock by four
for use as the main system clock in internal clock mode.
Peripheral Clock
The source for the main system clock in external clock mode. In
synchronous bus mode, all host bus signals are assumed to be
synchronous to this clock.
Analog
TTL-level Input, with Pull-up
TTL-level Input, with Schmitt Trigger
TTL-level Output
TTL-level Output (Open Drain)
Supply
TTL-level Input
TTL-level Input, with Pull-down
TTL-level Bidirectional Pin
TTL-level Output (Tristate)
Ground
Table 1: Pin Legend
Description
DS_8430_001
Rev. 1.2
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