ISPGDX240VA-4BN388 Lattice, ISPGDX240VA-4BN388 Datasheet - Page 7

• Manufacturer Part Number: ISPGDX240VA-4BN388
• Description: Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
• Manufacturer: Lattice

Specifications of ISPGDX240VA-4BN388

• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Single
• Configuration: 240 x 240
• Package / Case: PLCC-28
• Input Level: TTL
• Output Level: TTL
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5. Address Demultiplex/Data Buffering
Figure 6. Data Bus Byte Swapper
Figure 7. Four-Port Memory Interface
Applications (Continued)
Note: All OE and SEL lines driven by external arbiter logic (not shown).
D8-15
D0-7
I/OA
OEA OEB
I/OA
OEA OEB
XCVR
XCVR
I/OB
I/OB
I/OA
OEA
D
CLK
Address
XCVR
Latch
Port #1
OE1
Port #2
OE2
Port #3
OE3
Port #4
OE4
Bidirectional
16-Bit MUX
OEB
I/OB
4-to-1
Q
I/OA
OEA OEB
I/OA
OEA OEB
Memory
D8-15
D0-7
XCVR
XCVR
SEL0
SEL1
OEM
Port
I/OB
I/OB
Buffered
Data
Address
To Memory/
Peripherals
To
Memory
7
Designing with the ispGDXVA
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O A0-39 (240 I/O device), it is not
possible to use I/O A0 and I/O A9 in the same MUX
function. As previously discussed, data path functions
will be assigned early in the design process and these
restrictions are reasonable in order to optimize speed
and cost.
User Electronic Signature
The ispGDXVA Family includes dedicated User Elec-
tronic Signature (UES) E
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific com-
mand. This information can be read even when the
security cell is programmed.
Security
The ispGDXVA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
Specifications ispGDX240VA
2
CMOS storage to allow users