PI90LVB16LE Pericom Semiconductor, PI90LVB16LE Datasheet
PI90LVB16LE
Manufacturer Part Number
PI90LVB16LE
Description
Clock Drivers & Distribution 1:6 BLVDS to TTL Distribution
Manufacturer
Pericom Semiconductor
Datasheet
1.PI90LVB16LEX.pdf
(12 pages)
Specifications of PI90LVB16LE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Features
• Master/Slave clock selection in a backplane application
• 160 MHz operation (typical)
• 100ps duty cycle distortion (typical)
• 50ps channel to channel skew (typical)
• 3.3V power supply design
• Glitch-free power on at CLKI/O pins
• Low Power design (16mA @ 3.3V static)
• Accepts small swing (300mV typical) differential signal levels
• Industrial temperature operating range (–40°C to +85°C)
• Packaging: (Pb-free & Green available)
Driver Mode Truth Table
Function Diagram
O
— 24-pin TSSOP (L)
H
H
H
L
L
E
08-0295
D
H
L
L
L
L
E
n I
p
t u
C
d r
C
H
H
X
L
L
L
K
CLKI/0+
CLKI/0–
I
N
OE
DE
C
L
K
H
H
L
L
Z
I
O /
+
R
C
O
L
u
K
H
H
D
L
L
Z
p t
I
O /
t u
–
C
L
Delay
K
H
H
H
H
L
O
U
T
1
MUX
General Description
PI90LVB16 is a six-channel LVTTL clock distribution driver with 50
picosecond channel-to-channel skew. It translates one BLVDS
(Bus Low-Voltage Differential Signaling) input signal into six LVTTL-
compatible output signals for distribution to adjacent chips on the
same board. The PI90LVB16 accepts BLVDS (300mV typical) differ-
ential input levels, and translates them to 3V CMOS output levels.
The 160MHz PI90LVB16 can be the master clock, driving inputs of
other clock I/O pins in a multipoint environment. It can also drive
the BLVDS backplane with a separate channel acting as a return/
source LVTTL clock source. The master/slave clock selection of the
driving source is controlled by the CrdCLK
output enable pin OE, when high, forces all CLK
A backplane clock distribution network must be able to drive many
transmission line stubs. The Bus LVDS feature of the PI90LVB16 is
ideal for driving data transfers in large, high-performance backplane
system applications. The device can be used as a source synchro-
nous driver to distribute clock signals within data and telecommu-
nications systems.
Receive Mode Truth Table
L = Low Logic State; H = High Logic State; X = Irrelevant
Z = High Impedance
O
H
L
L
E
D
H
H
H
E
C
d r
C
X
X
X
L
Clock Buffer/Bus Transceiver
K
N I
n I
p
t u
C (
CrdCLK
CLK
CLK
CLK
L
K
OUT0
OUT1
OUT5
V
V
I
3V Bus LVDS 1-to-6
O /
D I
IN
D I
+
≤
– )
≥
X
–
C (
. 0
. 0
IN
7 0
L
7 0
K
and the DE pins. An
V
PI90LVB16
V
I
O /
OUT
) –
PS8536C
pins high.
C
O
L
u
K
p t
H
H
L
11/11/08
O
t u
U
T
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PI90LVB16LE Summary of contents
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... Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com 08-0295 .169 4.3 .177 4.5 .047 1.20 Max SEATING PLANE .002 0.05 .006 0.15 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com DESCRIPTION: 24-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L ...