DS26503LN Maxim Integrated Products, DS26503LN Datasheet - Page 3

• Manufacturer Part Number: DS26503LN
• Description: Timers & Support Products E1-T1-J1 BITS Elemen t T1-E1-J1 BITS Elem
• Manufacturer: Maxim Integrated Products
• Type: Clock Recoveryr

Specifications of DS26503LN

• Supply Voltage (max): 3.46 V
• Supply Voltage (min): 3.13 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 85 mA
• Package / Case: LQFP-64

9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
9.1
9.2
11.1
11.2
11.3
12.1
12.2
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
15.1
15.2
16.1
16.2
16.3
16.4
16.5
17.1
19.1
13.2.1 Receive Level Indicator.........................................................................................................78
13.2.2 Receive G.703 Section 10 Synchronization Signal...............................................................79
13.2.3 Monitor Mode ........................................................................................................................79
13.3.1 Transmit Short-Circuit Detector/Limiter.................................................................................80
13.3.2 Transmit Open-Circuit Detector ............................................................................................80
13.3.3 Transmit BPV Error Insertion ................................................................................................80
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode) ............................................80
17.1.1 Parallel Port Mode ..............................................................................................................105
17.1.2 SPI Serial Port Mode ..........................................................................................................105
E1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................46
I/O PIN CONFIGURATION OPTIONS..........................................................................................52
T1 SYNCHRONIZATION STATUS MESSAGE ...........................................................................55
E1 SYNCHRONIZATION STATUS MESSAGE ...........................................................................64
LINE INTERFACE UNIT (LIU)......................................................................................................77
LOOPBACK CONFIGURATION ..................................................................................................95
6312KHZ SYNCHRONIZATION INTERFACE .............................................................................96
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ................................97
FUNCTIONAL TIMING DIAGRAMS ..........................................................................................105
OPERATING PARAMETERS ....................................................................................................108
AC TIMING PARAMETERS AND DIAGRAMS..........................................................................110
E1 C
E1 I
P
T1 B
T
R
S
A
LIU O
LIU R
LIU T
MCLK P
J
CMI (C
LIU C
R
R
T
I
T
B
B
I
M
NSTRUCTION
DENTIFICATION
ITTER
ROCESSOR
RANSMIT
RANSMIT
EST
A
LTERNATE
OUNDARY
YPASS
ECEIVE
ECOMMENDED
ECEIVE
ULTIPLEXED
/S
NFORMATION
ONTROL
IT
I
RANSMITTER
R
ECEIVER
ONTROL
B
PERATION
-O
A
ODE
EGISTERS
IT
R
RE
TTENUATOR
RIENTED
BOC ...........................................................................................................................56
6312
A
EGISTER
BOC .........................................................................................................................55
6312
-S
CCESS
S
S
M
I
CAN
R
NTERFACE
A
CALER
R
ARK
B
K
R
/S
...........................................................................................................................78
EGISTERS
EGISTER
H
US
K
R
.........................................................................................................................78
EGISTERS
C
H
R
I
Z
.....................................................................................................................102
EGISTER
R
IRCUITS
C
B
I
B
.....................................................................................................................79
Z
...................................................................................................................102
...................................................................................................................110
EGISTERS
NVERSION
S
EGISTER
IT
ODE
ASED ON
S
..................................................................................................................80
..................................................................................................................80
YNCHRONIZATION
A
YNCHRONIZATION
CCESS
...........................................................................................................101
...........................................................................................................105
(BOC) C
...........................................................................................................46
..........................................................................................................82
..........................................................................................................90
.......................................................................................................102
......................................................................................................48
....................................................................................................102
) O
CRC4 M
B
ASED ON
PTION
ONTROLLER
ULTIFRAME
.......................................................................................81
I
NTERFACE
I
3 of 122
NTERFACE
D
OUBLE
............................................................................55
......................................................................64
-F
O
O
RAME
PERATION
PERATION
.........................................................74
...................................................96
.................................................96