SL28506BZI-2T Silicon Laboratories Inc, SL28506BZI-2T Datasheet - Page 10

• Manufacturer Part Number: SL28506BZI-2T
• Description: Clock Generators & Support Products CK505 v1.1 PCIe Gen2
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28506BZI-2T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.3 June 18, 2008
Byte 11 Control Register 11
Byte 12 Byte Count
Byte 13 Control Register 13
Bit
Bit
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
@Pup
@Pup
HW
0
1
0
1
1
0
0
0
0
1
1
0
1
1
1
0
0
1
1
1
CPU2_STP_CRTL
25MHz_EN_SE1
CPU2_AMT_EN
CPU1_AMT_EN
EN_CFG0_SET
PCI/PCIF_Bit1
SATA_SS_EN
SE1/SE2_Bit1
PCI-E_GEN2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
USB_Bit1
Name
Name
BC5
BC4
BC3
BC2
BC1
BC0
25MHz Output Enabled applies to Powerdown / M1
(Only applies when PCI3/CGFG0 strap is set high to enter HW mode 3)
0 = 25MHz disabled in Powerdown / M1
1 = 25MHz enabled in Powerdown / M1; Sticky 1
RESERVED
PCI-E_Gen2 Compliant
0 = non Gen2, 1= Gen2 Compliant
Allow control of CPU2 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
RESERVED
RESERVED
Byte count
Byte count
Byte count
Byte count
Byte count
Byte count
USB drive strength control, See Byte 18 for more setting
0 = Low, 1= High
PCI drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
RESERVED
Enable SATA spread modulation,
0 = Spread Disabled 1 = Spread Enabled
By defalult CFG0 pin strap sets the SMBus initial values to select the HW
mode. When this bit is written0, subsequent SMBus accesses is the Lathes
Open state, can overwrite the CFG0 pin setting into the SMBus bits and set
the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5
SE1 and SE2 drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
RESERVED
PCIF0/ITP_EN
x
x
1
1
AMT_EN
1
1
1
1
CPU2_AMT_EN
0
0
1
1
Description
Description
CPU1_AMT_EN
0
1
0
1
Page 10 of 28
Reserved
CPU1 = M1 Clock
CPU2 - M1 Clock
CPU1 and CPU2 = M1 Clock
SL28506-2
Description