CY28547LFXC Silicon Laboratories Inc, CY28547LFXC Datasheet - Page 3

• Manufacturer Part Number: CY28547LFXC
• Description: Clock Generators & Support Products CK505 Mobile System Clock
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28547LFXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
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32
33
34
37
39
40
41
42
43, 44
45
47, 48
50, 51
Pin No.
PCI2/TME
PCI3
PCI4/FCTSEL1
ITP_SEL/PCIF0
VTT_PWRGD#/PD
CKPWRGD/PD#
VDD_48
48M/FSA
VSS_48
DOT96T/ 27M_NSS
DOT96C/ 27M_SS
FSB/TEST_MODE
SRC[T/C]0/
LCD100M[T/C]
SRCT_1/SATAT,
SRCC_1/SATAC
(continued)
Name
I/O, SE 33-MHz clock output/Trusted Mode Enable Strap
I/O,SE 3.3V LVTTL input to enable SRC10 or CPU2_ITP/33-MHz clock output. (sampled
O, DIF Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output Selected
O, DIF 100-MHz Differential serial reference clocks.
O, SE 33-MHz clock output
O,DIF 100-MHz differential serial reference clock output/Differential 96/100-MHz SS
PWR 3.3V power supply for outputs.
GND
Type
I/O
I/O
I
I
Strap at pin 39 assertion to determine if the part is in trusted mode or not.
Internal pull-up resistor of 100K to 3.3V, use 10K resistor to pull it low externally
if needed
0 = Normal mode
1= Trusted mode (default)
33-MHz clock output/3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on pin 39 assertion).
Internal pull-down resistor of 100K to GND
on pin 39 assertion).
Internal pull-down resistor of 100K to GND
1 = CPU2_ITP, 0 = SRC10
3.3V LVTTL input. This pin is a level sensitive strobe. When asserted, according
to the polarity defined by pin 9 (PGMODE), it latches data on the FSA, FSB, FSC,
FCTSEL1 and ITP_SEL pins. After assertion, it becomes a real time input for
controlling power down.
Fixed 48-MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
via FCTSEL1 at pin 39 assertion.
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when
in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
clock for flat-panel display
Selected via FCTSEL1 at pin 39 assertion.
FCTS E L1 P in 43
PGMODE
0
0
1
1
0 DOT96T
1 27M_NSS
0 = POWER GOOD (VTT_PWRGD#)
1 = POWER DOWN (PD)
0 = POWER DOWN (PD#)
1 = POWER GOOD (CKPWRGD)
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
Pin 39
P in 44
DOT96C
27M_SS
Description
P in 47
96/100M_T 96/100M_C
SRCT0
P in 48
SRCC0
CY28547