CY28551LFXC Silicon Laboratories Inc, CY28551LFXC Datasheet - Page 18

• Manufacturer Part Number: CY28551LFXC
• Description: Clock Generators & Support Products Universal System Clk Intel AMD SiS Via
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28551LFXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.1, Faburary 1, 2008
CLKREQ# Clarification
The CLKREQ# signals are active LOW inputs used to cleanly
stop and start selected SRC outputs. The outputs controlled
by CLKREQ# are determined by the settings in register bytes
10 and 11. The CLKREQ# signal is a debounced signal in that
its state must remain unchanged during two consecutive rising
edges of DIFC to be recognized as a valid assertion or
deassertion. (The assertion and deassertion of this signal is
absolutely asynchronous.)
CLKREQ# Assertion
All differential outputs that were stopped will resume normal
operation in a glitch-free manner. The maximum latency from
the deassertion to active outputs is between 2 and 6 PCIEX
clock periods (2 clocks are shown) with all CLKREQ# outputs
resuming simultaneously. If the CLKREQ# drive mode is
tri-state, all stopped PCIEX outputs must be driven HIGH
PCIEXC (free running)
P C I E X 1 0 0 M H z
PCIEXT(free running)
P C I E X 1 0 0 M H z
PCIEXC(stoppable)
PCIEXT(stoppable)
P C I _ S T P #
P C I _ S T P #
P C I _ F
P C I _ F
PE_REQ #
P C I
P C I
T s u _ p c i _ s t p # >
1 0 n s
T d r i v e _ P C I E X < 1 5 n s
Figure 9. CLKREQ# Deassertion
Figure 7. PCI_STP# Assertion
Figure 8. PCI_STP# Deassertion
within 10 ns of CLKREQ# deassertion to a voltage greater than
200 mV.
CLKREQ# Deassertion
The impact of asserting the CLKREQ# pins is that all DIF
outputs that are set in the control registers to stoppable via
assertion of CLKREQ# are to be stopped after their next
transition. When the control register CLKREQ# drive mode bit
is programmed to '0', the final state of all stopped PCIEX
signals is PCIEXT clock = HIGH and PCIEXC = LOW. There
will be no change to the output drive current values. SRCT will
be driven HIGH with a current value equal 6 x Iref. When the
control register CLKREQ# drive mode bit is programmed to '1',
the final state of all stopped DIF signals is LOW; both PCIEXT
clock and PCIEXC clock outputs will not be driven.
Tdrive_PE_REQ #
< 10 ns
CY28551
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